topic Re: Mistake in UART4 Transmit Enable Register description for LPC1778 in LPCXpresso IDE

Mistake in UART4 Transmit Enable Register description for LPC1778

lpcware — Wed, 15 Jun 2016 22:56:27 GMT

Content originally posted in LPCWare by mgalemin on Tue Apr 03 18:16:42 MST 2012
Hi all,

I'm working with UARTs on LPC1778 microcontroller and I've noticed that there is a number of mistakes in description for U4TER UART4 Transmit Enable Register in UM10470 document. On page 478 U4TER has address 0x400A[COLOR=red]405C[/COLOR] and reset value 0x01, then on page 498 it has 0x400A[COLOR=Red]C05C[/COLOR] address, but on next page it has 0x400A[COLOR=red]4030[/COLOR] address. After some digging I found that reset values for these three registers are:

0x400A4030 = 0x80
0x400A405C = 0x00
0x400AC05C = 0x00

So I assume that offset and reset value for U4TER register is the same as for another UARTs (0/1/2/3), i.e. the correct address is 0x400A4030 and reset value is 0x80. Could you please confirm this or if I'm wrong could you please provide me with the correct address and reset value for the UART4 Transmit Enable Register? Thanks a lot in advance.

Cheers,
Max.

Re: Mistake in UART4 Transmit Enable Register description for LPC1778

lpcware — Wed, 15 Jun 2016 22:56:28 GMT

Content originally posted in LPCWare by capiman on Wed Apr 18 00:07:25 MST 2012
Looking into the CMSIS file LPC177x_8x.h (CMSIS Version 12302011),
delivered for LPC1778 on www.lpcware.com
(http://www.lpcware.com/content/nxpfile/lpc177x-and-lpc178x-cmsis-compliant-standard-peripheral-firmware-driver-library-keil)

it looks like U4TER is on 0x400A405C.

But file could also be wrong or i have done an error calculating the address.

#define LPC_APB1_BASE         (0x40080000UL)

#define LPC_UART4_BASE        (LPC_APB1_BASE + 0x24000)

__IO uint32_t TER;                   /*!< Offset: 0x05C Transmit Enable Register (R/W) */

BTW: There is an error in the comment of this file for UART4:

union {
__IO uint32_t DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
__IO uint32_t IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
};

shall be

union {
__IO uint32_t DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
__IO uint32_t IER;                   /*!< Offset: 0x004 Interrupt Enable Register (R/W) */
};

Re: Mistake in UART4 Transmit Enable Register description for LPC1778

lpcware — Wed, 15 Jun 2016 22:56:29 GMT

Content originally posted in LPCWare by NXP_Europe on Wed Apr 18 02:36:28 MST 2012
Hi,

Thanks for pointing out the problem, both the user manual and the comment in the LPC177x_8x.h are wrong indeed.

Let me do some research into this, I will come back on this shortly.

Regards,

Re: Mistake in UART4 Transmit Enable Register description for LPC1778

lpcware — Wed, 15 Jun 2016 22:56:29 GMT

Content originally posted in LPCWare by capiman on Thu Apr 26 23:46:10 MST 2012
Hello NXP_Europe,

can you tell me, if there is already an update on this topic?

Best regards,

Martin

Re: Mistake in UART4 Transmit Enable Register description for LPC1778

njleverton2 — Thu, 09 Feb 2017 10:42:13 GMT

This situation has got even more confusing over the last five years. The LPC177x/8x User Manual version 4.0 now says that UART4 does not have a TER at all, it is completely missing from the UART4 description. But it looks as if UART4, contrary to the manual, uses USART IP, and hence does have the TER at 0x5C. Note the TXEN bit will probably also be different for UART4 (0x01 not 0x80) for this reason. Maybe NXP could correct the documentation please ?