NXP: Multiplexed I/O Pins: Documentation Request

lpcware — Wed, 15 Jun 2016 21:29:59 GMT

Content originally posted in LPCWare by MikeSimmonds on Sun Nov 02 14:07:46 MST 2014
I appears (from various postings and UM's and personal experience) that at least some of the port
setup bits (pull up/down, hysteresis, slew etc. etc. are acted upon even when an alternate function
(i.e not GPIO) is selected for the pin.

For those of us who came to embedded design via the software route, can NXP publish MCU agnsotic
details of the best practice when setting up I/O pins (i.e. what pull up/down, fast slew, hysteresis, glitch
filter, open-drain, invert, etc.) should be used when selecting various I/O functionality such as:

SPI, I2C, SD card, LCD, External Memory Contoller Address/Data/Control, CAN, UART, Ethernet, USB,
ADC, DAC, I2S, and other built in peripherals in the various MCUs.

Manuals say what can be set, but not when and why!

For widest availability, this should be first an App Note, and second an lpcware blog.

And we should be discussing I/O pin capabilities without the confusion of actual IO register details
of reference to LPC Open or other headers -- The actual mechanics of implementing the settings
vary wildy amongst the MCU families and specific code examples will only confuse users who favour
devices from different families.

Strictly speaking, this is not NXP's problem; but surely helping newcommers to create sucessful and robust
designs will boost NXP's image and reputation, and increase chip sales in the hobyist arena.

Regards, Mike

Re: NXP: Multiplexed I/O Pins: Documentation Request

lpcware — Wed, 15 Jun 2016 21:30:00 GMT

Content originally posted in LPCWare by MikeSimmonds on Tue Nov 25 10:02:16 MST 2014
bump

topic Re: NXP: Multiplexed I/O Pins: Documentation Request in LPCXpresso IDE

NXP: Multiplexed I/O Pins: Documentation Request

Re: NXP: Multiplexed I/O Pins: Documentation Request