topic Re: LPC11xx Cortex-M0 Peripherals in LPCXpresso IDE https://community.nxp.com/t5/LPCXpresso-IDE/LPC11xx-Cortex-M0-Peripherals/m-p/593087#M30296 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by CodeRedSupport on Fri Mar 23 15:51:43 MST 2012</STRONG><BR /><SPAN>The VTOR register is typically seen as not existing on Cortex-M0. However the ARM v6M Architecture Reference Manual says the following....</SPAN><BR /><BR /><HR /><SPAN style="color: #0000ff;"><STRONG>Quote: </STRONG><BR />Vector Table Offset Register (VTOR)<BR />The vector table base address is fixed at 0x00000000. This register (address 0xE000ED08) is RAZ/WI for ARMv6-M.</SPAN><HR /><BR /><BR /><SPAN>[RAZ/WI = Read as zero, ignore writes].</SPAN><BR /><BR /><SPAN>You can find links to ARM's processor documentation here:</SPAN><BR /><BR /><A href="http://">http://support.code-red-tech.com/CodeRedWiki/ArmCpuInfo</A><BR /><BR /><SPAN>Regards,</SPAN><BR /><SPAN>CodeRedSupport</SPAN></BODY></HTML> Wed, 15 Jun 2016 22:52:24 GMT lpcware 2016-06-15T22:52:24Z LPC11xx Cortex-M0 Peripherals https://community.nxp.com/t5/LPCXpresso-IDE/LPC11xx-Cortex-M0-Peripherals/m-p/593086#M30295 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by ArtjomGromak on Tue Mar 20 11:26:12 MST 2012</STRONG><BR /><SPAN>Hi!</SPAN><BR /><SPAN>One question about debugging: in Peripherals NVIC regirters view (Memory NVIC selected) from address 0xE000ED08 placed register VECT_OFFSET.</SPAN><BR /><SPAN>It is error?</SPAN><BR /><SPAN>If not,&nbsp; where description of this register?</SPAN><BR /><BR /><SPAN>Thaks.</SPAN></BODY></HTML> Wed, 15 Jun 2016 22:52:23 GMT https://community.nxp.com/t5/LPCXpresso-IDE/LPC11xx-Cortex-M0-Peripherals/m-p/593086#M30295 lpcware 2016-06-15T22:52:23Z Re: LPC11xx Cortex-M0 Peripherals https://community.nxp.com/t5/LPCXpresso-IDE/LPC11xx-Cortex-M0-Peripherals/m-p/593087#M30296 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by CodeRedSupport on Fri Mar 23 15:51:43 MST 2012</STRONG><BR /><SPAN>The VTOR register is typically seen as not existing on Cortex-M0. However the ARM v6M Architecture Reference Manual says the following....</SPAN><BR /><BR /><HR /><SPAN style="color: #0000ff;"><STRONG>Quote: </STRONG><BR />Vector Table Offset Register (VTOR)<BR />The vector table base address is fixed at 0x00000000. This register (address 0xE000ED08) is RAZ/WI for ARMv6-M.</SPAN><HR /><BR /><BR /><SPAN>[RAZ/WI = Read as zero, ignore writes].</SPAN><BR /><BR /><SPAN>You can find links to ARM's processor documentation here:</SPAN><BR /><BR /><A href="http://">http://support.code-red-tech.com/CodeRedWiki/ArmCpuInfo</A><BR /><BR /><SPAN>Regards,</SPAN><BR /><SPAN>CodeRedSupport</SPAN></BODY></HTML> Wed, 15 Jun 2016 22:52:24 GMT https://community.nxp.com/t5/LPCXpresso-IDE/LPC11xx-Cortex-M0-Peripherals/m-p/593087#M30296 lpcware 2016-06-15T22:52:24Z