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    <title>LPCXpresso IDEのトピックLPC11A14 UART question</title>
    <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC11A14-UART-question/m-p/587638#M27733</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by tyassin on Tue Mar 04 06:11:52 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have read the datasheet for this device and have a question about IIR-register.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;In this register there is a flag in IIR[3:1] that can give you status of the UART. One of these flags are when IIR[3:1] is 0x3 'Receive Line Status (RLS)'. In this register, which now is called Line status register(LSR?????) is the first bit 0 'RDR(Receive Data Ready)' if there is data ready to be read from FIFO.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My question is what is the difference between this flag and the when the status of IIR[3:1] is 0x02 'Receive Data Available(RDA)'?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 22:48:39 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T22:48:39Z</dc:date>
    <item>
      <title>LPC11A14 UART question</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC11A14-UART-question/m-p/587638#M27733</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by tyassin on Tue Mar 04 06:11:52 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have read the datasheet for this device and have a question about IIR-register.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;In this register there is a flag in IIR[3:1] that can give you status of the UART. One of these flags are when IIR[3:1] is 0x3 'Receive Line Status (RLS)'. In this register, which now is called Line status register(LSR?????) is the first bit 0 'RDR(Receive Data Ready)' if there is data ready to be read from FIFO.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My question is what is the difference between this flag and the when the status of IIR[3:1] is 0x02 'Receive Data Available(RDA)'?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 22:48:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/LPC11A14-UART-question/m-p/587638#M27733</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T22:48:39Z</dc:date>
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