topic Re: lpc1764 + lan8720a, problem with packets in LPCXpresso IDE

lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:32 GMT

Content originally posted in LPCWare by rasiak on Tue Nov 27 07:58:20 MST 2012
Hi,

I'm running uIP example on my own pcb with lpc1764 and lan8720a. When I send packets via ethernet from uC to PC everything is fine, but in the other direction packets are distorted, eg:

PC sends:
ff ff ff ff ff ff bc ae c5 16 eb 89 08 06 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00

uC gets:
ff ff ff ff ff 7f bc 2e c5 14 6b 01 00 04 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 a4 4b d2

another,
PC sends:
ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00

uC gets:
ff ff ff ff ff ff ff ff ff ff ff 7f 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 04 55 14

Does anyone know what can be wrong?

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:33 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 01:18:54 MST 2012
I've noticed that there is a problem with transmitting even bits, eg:
ff =11111111
7f=[COLOR=Red]0[/COLOR]1111111

16=10110
14=101[COLOR=Red]0[/COLOR]0

ae=10101110
2e=[COLOR=Red]0[/COLOR]0101110

what do you think?

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:34 GMT

Content originally posted in LPCWare by serge on Thu Nov 29 04:50:54 MST 2012
Looks like a sync problem.

What about the crystal of the 8720a? is it oscilating on the right frequency?

In which mode do you use the 8720a? RMII?

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:34 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 06:55:44 MST 2012
25mhz, rmii mode, i'll paste codes here later..

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:35 GMT

Content originally posted in LPCWare by Ex-Zero on Thu Nov 29 07:15:46 MST 2012
Did you try your Code with another (not own PCB) board already to exclude hardware problems?

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:36 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 10:30:08 MST 2012
no, i don't have another board..
i've checked signals between lan8720 and lpc1764 and it looks fine(bytes are correct), so uC is faulty..

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:36 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 11:15:05 MST 2012
main.c

#define MYIP_1    192 
#define MYIP_2    168 
#define MYIP_3    0 
#define MYIP_4    100 
 
 
#include "LPC17xx.h" 
 
#include "timer.h" 
#include "uip.h" 
#include "uip_arp.h" 
#include "tapdev.h" 
 
#include <cr_section_macros.h> 
#include <NXP/crp.h> 
// Variable to store CRP value in. Will be placed automatically 
// by the linker when "Enable Code Read Protect" selected. 
// See crp.h header for more information 
__CRP const unsigned int CRP_WORD = CRP_NO_CRP ; 
 
#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) 
 
void uip_log(char *m) 
{ 
  //printf("uIP log message: %s\n", m); 
} 
 
char ipstring [20]; 
 
int main(void) 
{ 
    unsigned int i; 
    uip_ipaddr_t ipaddr;    /* local IP address */ 
    struct timer periodic_timer, arp_timer; 
 
    // Code Red - if CMSIS is being used, then SystemInit() routine 
    // will be called by startup code rather than in application's main() 
//#ifndef __USE_CMSIS 
    // system init 
    SystemInit();    /* setup core clocks */ 
    printf("systemInit"); 
//#endif 
 
    // clock init 
    clock_init(); 
        // two timers for tcp/ip 
    timer_set(&periodic_timer, CLOCK_SECOND / 2); /* 0.5s */ 
    timer_set(&arp_timer, CLOCK_SECOND * 10);    /* 10s */ 
     
    // ethernet init 
    tapdev_init(); 
 
    // Initialize the uIP TCP/IP stack. 
//    uip_init(); 
 
//    uip_ipaddr(ipaddr, MYIP_1,MYIP_2,MYIP_3,MYIP_4); 
//    uip_sethostaddr(ipaddr);    /* host IP address */ 
//    uip_ipaddr(ipaddr, MYIP_1,MYIP_2,MYIP_3,1); 
//    uip_setdraddr(ipaddr);    /* router IP address */ 
//    uip_ipaddr(ipaddr, 255,255,255,0); 
//    uip_setnetmask(ipaddr);    /* mask */ 
 
    // Initialize the HTTP server, listen to port 80. 
    httpd_init(); 
printf("httpd_init"); 
 
SystemCoreClockUpdate (); 
printf("SystemCoreClock: %d\n", SystemCoreClock); 
 
int abc=0; 
    while(1) 
    { 
     /* receive packet and put in uip_buf */ 
        uip_len = tapdev_read(uip_buf); 
        if(uip_len > 0)        /* received packet */ 
        {  
            printf("pakiet "); 
            for(abc=0;abc<uip_len;abc++)printf("%x ",uip_buf[abc]); 
            printf("\n"); 
 
//--------------------------------------------- 
            tapdev_send(uip_buf,uip_len); 
            tapdev_send("jakis tekst ktory ma sprwadzic dzialanie przesylania danych po porcie ethernet",78); 
//----------------------------------------- 
              if(BUF->type == htons(UIP_ETHTYPE_IP))    /* IP packet */ 
              { 
                  printf("IP"); 
                  uip_arp_ipin();     
                  uip_input(); 
                  /* If the above function invocation resulted in data that 
                     should be sent out on the network, the global variable 
                     uip_len is set to a value > 0. */ 
  
                  if(uip_len > 0) 
                { 
                      uip_arp_out(); 
                    tapdev_send(uip_buf,uip_len); 
                  } 
              } 
              else if(BUF->type == htons(UIP_ETHTYPE_ARP))    /*ARP packet */ 
              { 
                  printf("ARP"); 
                uip_arp_arpin(); 
                  /* If the above function invocation resulted in data that 
                     should be sent out on the network, the global variable 
                     uip_len is set to a value > 0. */ 
                  if(uip_len > 0) 
                { 
                    tapdev_send(uip_buf,uip_len);    /* ARP ack*/ 
                  } 
              } 
        } 
        else if(timer_expired(&periodic_timer))    /* no packet but periodic_timer time out (0.5s)*/ 
        { 
              timer_reset(&periodic_timer); 
       
              for(i = 0; i < UIP_CONNS; i++) 
              { 
                  uip_periodic(i); 
                /* If the above function invocation resulted in data that 
                   should be sent out on the network, the global variable 
                   uip_len is set to a value > 0. */ 
                if(uip_len > 0) 
                { 
                  uip_arp_out(); 
                  tapdev_send(uip_buf,uip_len); 
                } 
              } 
#if UIP_UDP 
            for(i = 0; i < UIP_UDP_CONNS; i++) { 
                uip_udp_periodic(i); 
                /* If the above function invocation resulted in data that 
                   should be sent out on the network, the global variable 
                   uip_len is set to a value > 0. */ 
                if(uip_len > 0) { 
                  uip_arp_out(); 
                  tapdev_send(); 
                } 
            } 
#endif /* UIP_UDP */ 
             /* Call the ARP timer function every 10 seconds. */ 
            if(timer_expired(&arp_timer)) 
            { 
                //timer_reset(&arp_timer); 
                //uip_arp_timer(); 
            } 
        } 
    } 
}

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:37 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 11:15:56 MST 2012
lpc17xx_emac.c

// ********************************************************************* 
// Define the IP address to be used for the MCU running the TCP/IP stack 
// ********************************************************************* 
#define MYIP_1    192 
#define MYIP_2    168 
#define MYIP_3    0 
#define MYIP_4    100 
 
 
#include "LPC17xx.h" 
 
#include "timer.h" 
#include "uip.h" 
#include "uip_arp.h" 
#include "tapdev.h" 
 
#include <cr_section_macros.h> 
#include <NXP/crp.h> 
// Variable to store CRP value in. Will be placed automatically 
// by the linker when "Enable Code Read Protect" selected. 
// See crp.h header for more information 
__CRP const unsigned int CRP_WORD = CRP_NO_CRP ; 
 
#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) 
 
void uip_log(char *m) 
{ 
  //printf("uIP log message: %s\n", m); 
} 
 
char ipstring [20]; 
 
int main(void) 
{ 
    unsigned int i; 
    uip_ipaddr_t ipaddr;    /* local IP address */ 
    struct timer periodic_timer, arp_timer; 
 
    // Code Red - if CMSIS is being used, then SystemInit() routine 
    // will be called by startup code rather than in application's main() 
//#ifndef __USE_CMSIS 
    // system init 
    SystemInit();    /* setup core clocks */ 
    printf("systemInit"); 
//#endif 
 
    // clock init 
    clock_init(); 
        // two timers for tcp/ip 
    timer_set(&periodic_timer, CLOCK_SECOND / 2); /* 0.5s */ 
    timer_set(&arp_timer, CLOCK_SECOND * 10);    /* 10s */ 
     
    // ethernet init 
    tapdev_init(); 
 
    // Initialize the uIP TCP/IP stack. 
//    uip_init(); 
 
//    uip_ipaddr(ipaddr, MYIP_1,MYIP_2,MYIP_3,MYIP_4); 
//    uip_sethostaddr(ipaddr);    /* host IP address */ 
//    uip_ipaddr(ipaddr, MYIP_1,MYIP_2,MYIP_3,1); 
//    uip_setdraddr(ipaddr);    /* router IP address */ 
//    uip_ipaddr(ipaddr, 255,255,255,0); 
//    uip_setnetmask(ipaddr);    /* mask */ 
 
    // Initialize the HTTP server, listen to port 80. 
    httpd_init(); 
printf("httpd_init"); 
 
SystemCoreClockUpdate (); 
printf("SystemCoreClock: %d\n", SystemCoreClock); 
 
int abc=0; 
    while(1) 
    { 
     /* receive packet and put in uip_buf */ 
        uip_len = tapdev_read(uip_buf); 
        if(uip_len > 0)        /* received packet */ 
        {  
            printf("pakiet "); 
            for(abc=0;abc<uip_len;abc++)printf("%x ",uip_buf[abc]); 
            printf("\n"); 
 
//--------------------------------------------- 
            tapdev_send(uip_buf,uip_len); 
            tapdev_send("jakis tekst ktory ma sprwadzic dzialanie przesylania danych po porcie ethernet",78); 
//----------------------------------------- 
              if(BUF->type == htons(UIP_ETHTYPE_IP))    /* IP packet */ 
              { 
                  printf("IP"); 
                  uip_arp_ipin();     
                  uip_input(); 
                  /* If the above function invocation resulted in data that 
                     should be sent out on the network, the global variable 
                     uip_len is set to a value > 0. */ 
  
                  if(uip_len > 0) 
                { 
                      uip_arp_out(); 
                    tapdev_send(uip_buf,uip_len); 
                  } 
              } 
              else if(BUF->type == htons(UIP_ETHTYPE_ARP))    /*ARP packet */ 
              { 
                  printf("ARP"); 
                uip_arp_arpin(); 
                  /* If the above function invocation resulted in data that 
                     should be sent out on the network, the global variable 
                     uip_len is set to a value > 0. */ 
                  if(uip_len > 0) 
                { 
                    tapdev_send(uip_buf,uip_len);    /* ARP ack*/ 
                  } 
              } 
        } 
        else if(timer_expired(&periodic_timer))    /* no packet but periodic_timer time out (0.5s)*/ 
        { 
              timer_reset(&periodic_timer); 
       
              for(i = 0; i < UIP_CONNS; i++) 
              { 
                  uip_periodic(i); 
                /* If the above function invocation resulted in data that 
                   should be sent out on the network, the global variable 
                   uip_len is set to a value > 0. */ 
                if(uip_len > 0) 
                { 
                  uip_arp_out(); 
                  tapdev_send(uip_buf,uip_len); 
                } 
              } 
#if UIP_UDP 
            for(i = 0; i < UIP_UDP_CONNS; i++) { 
                uip_udp_periodic(i); 
                /* If the above function invocation resulted in data that 
                   should be sent out on the network, the global variable 
                   uip_len is set to a value > 0. */ 
                if(uip_len > 0) { 
                  uip_arp_out(); 
                  tapdev_send(); 
                } 
            } 
#endif /* UIP_UDP */ 
             /* Call the ARP timer function every 10 seconds. */ 
            if(timer_expired(&arp_timer)) 
            { 
                //timer_reset(&arp_timer); 
                //uip_arp_timer(); 
            } 
        } 
    } 
}

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:38 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 11:19:39 MST 2012
system_LPC17xx.c

  #include <stdint.h> 
  #include "LPC17xx.h" 
   
  #define CLOCK_SETUP           1 
  #define SCS_Val               0x00000020 
  #define CLKSRCSEL_Val         0x00000001 
  #define PLL0_SETUP            1 
  #define PLL0CFG_Val           0x00000018 // 100MHz //0x00110132 
  #define PLL1_SETUP            1 
  #define PLL1CFG_Val           0x00000023 
  #define CCLKCFG_Val           0x00000003 
  #define USBCLKCFG_Val         0x00000000 
  #define PCLKSEL0_Val          0x00000000 
  #define PCLKSEL1_Val          0x00000000 
  #define PCONP_Val             0x042887DE 
  #define CLKOUTCFG_Val         0x00000000 
  
  // 
  // <e> Flash Accelerator Configuration 
  //   <o1.12..15> FLASHTIM: Flash Access Time 
  //               <0=> 1 CPU clock (for CPU clock up to 20 MHz) 
  //               <1=> 2 CPU clocks (for CPU clock up to 40 MHz) 
  //               <2=> 3 CPU clocks (for CPU clock up to 60 MHz) 
  //               <3=> 4 CPU clocks (for CPU clock up to 80 MHz) 
  //               <4=> 5 CPU clocks (for CPU clock up to 100 MHz) 
  //               <5=> 6 CPU clocks (for any CPU clock) 
  // </e> 
  */ 
  #define FLASH_SETUP           1 //1 
  #define FLASHCFG_Val          0x00004000 

   
  /*---------------------------------------------------------------------------- 
    Check the register settings 
   *----------------------------------------------------------------------------*/ 
  #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max)) 
  #define CHECK_RSVD(val, mask)                     (val & mask) 
   
  /* Clock Configuration -------------------------------------------------------*/ 
  #if (CHECK_RSVD((SCS_Val),       ~0x00000030)) 
     #error "SCS: Invalid values of reserved bits!" 
  #endif 
   
  #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) 
     #error "CLKSRCSEL: Value out of range!" 
  #endif 
   
  #if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF)) 
     #error "PLL0CFG: Invalid values of reserved bits!" 
  #endif 
   
  #if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F)) 
     #error "PLL1CFG: Invalid values of reserved bits!" 
  #endif 
   
  #if (PLL0_SETUP)            /* if PLL0 is used */ 
    #if (CCLKCFG_Val < 2)     /* CCLKSEL must be greater then 1 */ 
      #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" 
    #endif 
  #endif 
   
  #if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) 
     #error "CCLKCFG: Value out of range!" 
  #endif 
   
  #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) 
     #error "USBCLKCFG: Invalid values of reserved bits!" 
  #endif 
   
  #if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00)) 
     #error "PCLKSEL0: Invalid values of reserved bits!" 
  #endif 
   
  #if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300)) 
     #error "PCLKSEL1: Invalid values of reserved bits!" 
  #endif 
   
  #if (CHECK_RSVD((PCONP_Val),      0x10100821)) 
     #error "PCONP: Invalid values of reserved bits!" 
  #endif 
   
  #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) 
     #error "CLKOUTCFG: Invalid values of reserved bits!" 
  #endif 
   
  /* Flash Accelerator Configuration -------------------------------------------*/ 
  #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) 
     #error "FLASHCFG: Invalid values of reserved bits!" 
  #endif 
   
   
  /*---------------------------------------------------------------------------- 
    DEFINES 
   *----------------------------------------------------------------------------*/ 
       
  /*---------------------------------------------------------------------------- 
    Define clocks 
   *----------------------------------------------------------------------------*/ 
  #define XTAL        (8000000UL)        /* Oscillator frequency               */ 
  #define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */ 
  #define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */ 
  #define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */ 
   
   
  /* F_cco0 = (2 * M * F_in) / N  */ 
  #define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1) 
  #define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1) 
  #define __FCCO(__F_IN)    ((2 * __M * __F_IN) / __N)  
  #define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1) 
   
  /* Determine core clock frequency according to settings */ 
   #if (PLL0_SETUP) 
      #if   ((CLKSRCSEL_Val & 0x03) == 1) 
          #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) 
      #elif ((CLKSRCSEL_Val & 0x03) == 2) 
          #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) 
      #else  
          #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) 
      #endif 
   #else 
      #if   ((CLKSRCSEL_Val & 0x03) == 1) 
          #define __CORE_CLK (OSC_CLK         / __CCLK_DIV) 
      #elif ((CLKSRCSEL_Val & 0x03) == 2) 
          #define __CORE_CLK (RTC_CLK         / __CCLK_DIV) 
      #else 
          #define __CORE_CLK (IRC_OSC         / __CCLK_DIV) 
      #endif 
   #endif 
   
   
  /*---------------------------------------------------------------------------- 
    Clock Variable definitions 
   *----------------------------------------------------------------------------*/ 
  uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ 
   
   
  /*------------------------------------------------
    Clock functions 
   *----------------------------------------------------------------------------*/ 
  void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */ 
  { 
    /* Determine clock frequency according to clock register values             */ 
    if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ 
      switch (LPC_SC->CLKSRCSEL & 0x03) { 
        case 0:                                /* Int. RC oscillator => PLL0    */ 
        case 3:                                /* Reserved, default to Int. RC  */ 
          SystemCoreClock = (IRC_OSC *  
                            ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  / 
                            (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    / 
                            ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 
          break; 
        case 1:                                /* Main oscillator => PLL0       */ 
          SystemCoreClock = (OSC_CLK *  
                            ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  / 
                            (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    / 
                            ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 
          break; 
        case 2:                                /* RTC oscillator => PLL0        */ 
          SystemCoreClock = (RTC_CLK *  
                            ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  / 
                            (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    / 
                            ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 
          break; 
      } 
    } else { 
      switch (LPC_SC->CLKSRCSEL & 0x03) { 
        case 0:                                /* Int. RC oscillator => PLL0    */ 
        case 3:                                /* Reserved, default to Int. RC  */ 
          SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 
          break; 
        case 1:                                /* Main oscillator => PLL0       */ 
          SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 
          break; 
        case 2:                                /* RTC oscillator => PLL0        */ 
          SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 
          break; 
      } 
    } 
   
  } 
   
  
  void SystemInit (void) 
  { 
  #if (CLOCK_SETUP)                       /* Clock Setup                        */ 
    LPC_SC->SCS       = SCS_Val; 
    if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */ 
      while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */ 
    } 
   
    LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */ 
   
    LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */ 
    LPC_SC->PCLKSEL1  = PCLKSEL1_Val; 
   
    LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */ 
   
  #if (PLL0_SETUP) 
    LPC_SC->PLL0CFG   = PLL0CFG_Val;      /* configure PLL0                     */ 
    LPC_SC->PLL0FEED  = 0xAA; 
    LPC_SC->PLL0FEED  = 0x55; 
   
    LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */ 
    LPC_SC->PLL0FEED  = 0xAA; 
    LPC_SC->PLL0FEED  = 0x55; 
    while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */ 
   
    LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */ 
    LPC_SC->PLL0FEED  = 0xAA; 
    LPC_SC->PLL0FEED  = 0x55; 
    while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ 
  #endif 
   
  #if (PLL1_SETUP) 
    LPC_SC->PLL1CFG   = PLL1CFG_Val; 
    LPC_SC->PLL1FEED  = 0xAA; 
    LPC_SC->PLL1FEED  = 0x55; 
   
    LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */ 
    LPC_SC->PLL1FEED  = 0xAA; 
    LPC_SC->PLL1FEED  = 0x55; 
    while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */ 
   
    LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */ 
    LPC_SC->PLL1FEED  = 0xAA; 
    LPC_SC->PLL1FEED  = 0x55; 
    while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ 
  #else 
    LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */ 
  #endif 
   
    LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */ 
   
    LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */ 
  #endif 
   
  #if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */ 
    LPC_SC->FLASHCFG  = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; 
  #endif 
  }

uC is set on 100Mhz, is it enough??

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:38 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 11:22:07 MST 2012
lpc17xx_emac.h

...
/* LAN8720 PHY Registers */ 
#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */ 
#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */ 
#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */ 
#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */ 
#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */ 
#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */ 
#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */ 
 
/* PHY Extended Registers */ 
#define    PHY_REG_MODE_CTRL        17 
#define    PHY_REG_SPECIAL_MODE    18 
#define    PHY_REG_SYMBOL_ERR_CNT    26 
#define    PHY_REG_SPECIAL_CTRL    27 
#define    PHY_REG_INT_SOURCE        29 
#define    PHY_REG_INT_MASK        30 
#define    PHY_REG_PHY_CTRL        31 
 
#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */ 
#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */ 
#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */ 
#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */ 
#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */ 
//#define PHY_AUTO_NEG_COMPLETE 0x0020    /* Auto negotiation have finished.   */ 
 
 
 
//#define PHY_AUTO_NEG            0x3000  /* Select Auto Negotiation           */ 
#define PHY_AUTO_NEG_COMPLETE     0x1000    /* Auto negotiation have finished.   */ 
#define PHY_SPEED_FDUPLX         0x0010    /* Full Duplex   */ 
#define PHY_SPEED_100             0x0008    /* 100Mbit   */ 
 
#define LAN8720_DEF_ADR        0x0100      /* Default PHY device address        */ 
#define LAN8720_ID          0x0007C0F0  /* PHY Identifier                    */ 
#else 
    #error "No board" 
#endif 
 
#endif

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:39 GMT

Content originally posted in LPCWare by Ex-Zero on Thu Nov 29 12:17:01 MST 2012

Quote: rasiak
i've checked signals between lan8720 and lpc1764 and it looks fine(bytes are correct), so uC is faulty..

:confused: Sorry, can't follow you.

Perhaps you want to export and post your complete project so someone can test it with a standard 1768 & LAN8720 ;)

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:40 GMT

Content originally posted in LPCWare by rasiak on Thu Nov 29 17:05:20 MST 2012

Quote:
Perhaps you want to export and post your complete project so someone can test it with a standard 1768 & LAN8720 ;)

Actually I would be happy if someone who already did ethernet connection could check this code and give me an advice what to change :rolleyes:

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:40 GMT

Content originally posted in LPCWare by yanvasilij on Fri Nov 30 04:20:42 MST 2012
In some boards there is problem with schematics like this www.utasker.com/forum/index.php?topic=579.5;wap2. It occur crc-error.

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:41 GMT

Content originally posted in LPCWare by rasiak on Sun Dec 02 14:07:06 MST 2012
This is my code packed in one zip file... [ATTACH]896[/ATTACH]
If someone could test it with lpc17xx and lan8720, it would be great :rolleyes:

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:41 GMT

Content originally posted in LPCWare by Ex-Zero on Sun Dec 02 15:49:20 MST 2012
Obviously you are not running LAN8720 Code in your EMAC_Init :mad:

That's no link check, that's an autonegotiate check (which was already done before) :confused:

  /* Check the link status. */
  for (tout = 0; tout < 0x10000; tout++) {
    regv = read_PHY (PHY_REG_PHY_CTRL);
    if (regv & PHY_AUTO_NEG_COMPLETE)
    {       
      /* Link is on. */
        printf("Link is on\n");
      break;
    }
  }

A correct link test is:

  // Now check the link status LAN
   value = udp_readPHY (PHY_REG_BMSR);
   if (value & 0x0004)
   {
// The link is on
    break;
   }

Also Duplex reading is wrong:

 if (regv & PHY_SPEED_FDUPLX)
  {
    /* Full duplex is enabled. */
      printf("full duplex\n");
      LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
      LPC_EMAC->Command |= CR_FULL_DUP;
      LPC_EMAC->IPGT     = IPGT_FULL_DUP;
  }
  else {
    /* Half duplex mode. */
      printf("half duplex\n");
      LPC_EMAC->IPGT = IPGT_HALF_DUP;

Correct Duplex reading is:

 value = udp_readPHY(PHY_REG_SPECIAL);
// Now configure for full/half duplex mode
  if (value & 0b10000)
  {
// We are in full duplex is enabled mode
   LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
   LPC_EMAC->Command |= CR_FULL_DUP;
   LPC_EMAC->IPGT     = IPGT_FULL_DUP;
  }
  else
  {
// Otherwise we are in half duplex mode
   LPC_EMAC->IPGT = IPGT_HALF_DUP;
  }

Speed reading is wrong:

 /* Configure 100MBit/10MBit mode. */
  if (!(regv & PHY_SPEED_100))
  {
    /* 10MBit mode. */
      printf("10mbit\n");
      LPC_EMAC->SUPP = 0;
  }
  else {
    /* 100MBit mode. */
      printf("100mbit\n");
      LPC_EMAC->SUPP = SUPP_SPEED;
  }

Correct reading is:

 value = udp_readPHY(PHY_REG_SPECIAL);
...
// Now configure 100MBit or 10MBit mode
  if (value & 0b01000)
  {
// 100MBit mode
   LPC_EMAC->SUPP = SUPP_SPEED;
  }
  else
  {
// 10MBit mode
   LPC_EMAC->SUPP = 0;
  }
 }

[B][COLOR=Red]So whatever you init, it's not a LAN8720[/COLOR][/B] (http://www.smsc.com/media/Downloads_Public/Data_Sheets/8720a.pdf) :eek:

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:42 GMT

Content originally posted in LPCWare by rasiak on Tue Dec 04 14:52:04 MST 2012
ok, you're right :/ this is better version [ATTACH]897[/ATTACH], still not working(errors in some bits), could you run this?
ps. on my pcb there is no inverter on REFCLK pin(LAN8720), is it necessary?? (RDB1768 DEVELOPMENT BOARD has it)

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:42 GMT

Content originally posted in LPCWare by Luis Digital on Tue Dec 04 15:00:12 MST 2012

Quote: rasiak
ps. on my pcb there is no inverter on REFCLK pin(LAN8720), is it necessary?? (RDB1768 DEVELOPMENT BOARD has it)

I remarked that it was necessary, when I was building my LPC1764 board.

Although I have seen some designs that do not include it.

Edit: Oh, my board is available again, now 3!!!

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:43 GMT

Content originally posted in LPCWare by Ex-Zero on Wed Dec 05 12:02:08 MST 2012

Quote: rasiak
ok, you're right

this is better version

You're kidding

EMAC init isn't working because of wrong LAN8720_DEF_ADR :mad:

Who has mutilated this? Use correct:

 #define LAN8720_DEF_ADR        0x0100

Quote: rasiak
still not working(errors in some bits), could you run this?

No, I can't. Your included CMSIS1.3 is awful :mad: Use new CMSIS2.0. Which crystal are you using und which main clock are you trying to generate.

I think your main problem is your cheesy clock setup :eek:

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:44 GMT

Content originally posted in LPCWare by rasiak on Wed Dec 05 16:13:06 MST 2012

Quote:
You're kidding :) EMAC init isn't working because of wrong LAN8720_DEF_ADR
Who has mutilated this? Use correct:
Code:
#define LAN8720_DEF_ADR 0x0100

It's not workning, on my pcb PHYADR is 0 :D

Quote:
Your included CMSIS1.3 is awful :mad: Use new CMSIS2.0.

As You wish ;): [ATTACH]898[/ATTACH]

Re: lpc1764 + lan8720a, problem with packets

lpcware — Thu, 16 Jun 2016 01:16:44 GMT

Content originally posted in LPCWare by Ex-Zero on Wed Dec 05 16:17:07 MST 2012

Quote: Zero
Which crystal are you using und which main clock are you trying to generate :confused:

I'm still missing your clock data :(