topic Peripheral register access, RESERVED registers in LPCXpresso IDE

Peripheral register access, RESERVED registers

lpcware — Thu, 16 Jun 2016 01:15:01 GMT

Content originally posted in LPCWare by curtvm on Sun Nov 07 08:12:03 MST 2010
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LPC11xx manual
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2.2 Memory map-
All peripheral register addresses are 32-bit word aligned regardless of their size. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.
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I am unclear as to what this means. It seems to me the 'implication' is that since these registers are word aligned, they CAN be accessed as a word. The Cortex M0 requires word alignment for word access, halfword alignment for halfword access, and of course no alignment for byte access.

These registers cannot be accessed on a byte level?

The other part of this, is RESERVED bits in registers. Some have specific values that need to be written (like PDRUNCFG), some have non-zero reset values (like IOCON_PIOx_x), but no mention of whether writing 0 will cause problems, and the rest seem to be 0 on reset (not a problem).

So in some cases avoiding the reserved bits in registers by using byte access could be beneficial (maybe not that many). In the case of something like PDRUNCFG, it would usually make no difference since setting/clearing individual bits (Read-Modify-Write) would be the normal way to access these anyway (unless you set all bits as needed in one write).

So, can these registers be accessed on a byte level, and what is the story on writing 0's to reserved bits that are not 0 at reset (that show no required set value in datasheet description)?

Thanks.

update-
It appears reading/writing to peripheral registers does work with byte access. I only tested a few, but reading/writing bytes on some of these works ok (at least no hard faults, and results were as expected). I don't know if this holds true for AHB, though.

Re: Peripheral register access, RESERVED registers

lpcware — Thu, 16 Jun 2016 01:15:01 GMT

Content originally posted in LPCWare by CodeRedSupport on Mon Nov 08 14:52:28 MST 2010
I would recommend using a read/modify/write strategy to ensure that you basically only change the bits you actually want to change. The following example code (taken from http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS) shows this being done....

    #include "LPC17xx.h"

    // PCADC / PCAD
    #define ADC_POWERON (1 << 12)

    #define PCLK_ADC 24
    #define PCLK_ADC_MASK (3 << 24)

    // AD0.0 - P0.23, PINSEL1 [15:14] = 01
    #define SELECT_ADC0 (0x1<<14)
     :
    // Turn on power to ADC block
    LPC_SC->PCONP |=  ADC_POWERON;

    // Turn on ADC peripheral clock
    LPC_SC->PCLKSEL0 &= ~(PCLK_ADC_MASK);
    LPC_SC->PCLKSEL0 |=  (3 << PCLK_ADC);

    // Set P0.23 to AD0.0 in PINSEL1
    LPC_PINCON->PINSEL1 |= SELECT_ADC0;
      :

Regards,
CodeRedSupport

Re: Peripheral register access, RESERVED registers

lpcware — Thu, 16 Jun 2016 01:15:02 GMT

Content originally posted in LPCWare by curtvm on Mon Nov 08 15:48:39 MST 2010
That would be the smart thing to do, it seems.

Although it does look like there may be cases where that may cause problems if one is not careful. As in something like U0IER where bits 31:10 are described as 'Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.'

If the read of those bits is not defined, I suppose the possibility exists that the read could produce 1's, which then will be written. So in this case, I guess those bits need to be cleared also (Read-Modify-Modify-Write).

So, I guess in summary, these registers can be accessed at a byte level if needed (to avoid reserved bits for example, although it may not be worth the trouble). Reserved bits need to be written as instructed, if instructed in the register description. Reserved bits without any specific instructions, I guess the rule is nobody really knows, so just read-modify-write to avoid any surprises or potential strange problems.