topic LPC1769_100MHz core clock (?) in LPCXpresso IDE

LPC1769_100MHz core clock (?)

lpcware — Thu, 16 Jun 2016 02:33:48 GMT

Content originally posted in LPCWare by timos2302 on Mon Jun 20 15:07:40 MST 2011
[FONT=Century Gothic]Dear friends
I have read the UM datasheet, the blinky example, the timers example e.t.c , even the xls calculator given by NXP for calculating M, and N portions of the 32bit register configuration for the PLL0.

So i collected 3 questions/notes (sorry if they seem to childish for some of you)

-1- The M and N values that the xls calculator exports are true or the UM is true that says in small letters >>>> N-1, M-1 ? ? ?

-2-Suppose i want a 100MHz core clock >> AFTER the prescaller of the main clock, What on earth are your M and N values and prescaller settings with a 12MHz external clock ? I managed core clock (cclk) only up to 33.3MHz (cclk/3 - 100/3 - the /1 and /2 values are forbiden as i read).

-3- Is there a magic tool in excel or VB or something so i can get my hex value of the PLL0CGF register at once , and not breaking my head to combine the M,N portions and some dummy bits of this 32bit register, then converting in binary, then converting it into a hex monsterous byte?

Thanks all for your kind patience
Sincerely,
Timothy

(newbie to ARM's . . .:o comming from the AVR "poor" 8bit world)[/FONT]

Re: LPC1769_100MHz core clock (?)

lpcware — Thu, 16 Jun 2016 02:33:48 GMT

Content originally posted in LPCWare by Ex-Zero on Tue Jun 21 04:49:11 MST 2011
If you use CMSIS your clock setup is done in SystemInit() (...\CMSISv1p30_LPC17xx\src\system_LPC17xx.c).

There's also a short description of M,N,MSEL and NSEL and default setup should be 100MHz.

With:

#define PLL0CFG_Val  0x00050063
#define CCLKCFG_Val  0x00000003

you should be able to change your clock settings wihout magic

Re: LPC1769_100MHz core clock (?)

lpcware — Thu, 16 Jun 2016 02:33:49 GMT

Content originally posted in LPCWare by timos2302 on Tue Jun 21 12:03:09 MST 2011
thanks , that really helped :)