topic Re: Lpc1769 ADC+USB+SSP in LPCXpresso IDE

Lpc1769 ADC+USB+SSP

lpcware — Thu, 16 Jun 2016 02:26:43 GMT

Content originally posted in LPCWare by ranaya on Fri Jun 22 04:37:52 MST 2012
hello every1....

While doing some experiments with ADC and USB, I added an ADC code to the usb cdc code. My main objective is sampling some analogs after configuring the device(a usb datalogger) via usb. I think both adc and usb use interrupt handling. But in my adc code I use polling method.

int main (void) {
    DSTATUS stat;
    FIL * fpp ;
    BYTE  Float_STR[10] ;
    char comnd[64];
    LPC_GPIO0->FIODIR = 0x00400000;/* P2.xx defined as Outputs */
    LPC_GPIO0->FIOCLR = 0x00400000;

    SystemClockUpdate();
    VCOM_Init();

    ADCInit(ADC_CLK); //problem here !!!
    USB_Init();
    //init_ssp();
    delayMs(0,500) ;

    //stat = disk_initialize(0);
    //res = f_mount(0, &Fatfs[0]);
    USB_Connect(TRUE);

    while (!USB_Configuration) ;

    while (1) {
        USB2Usb(comnd);
        if(comnd[1]=='k'){
           LPC_GPIO0->FIOSET = 0x00400000;
           for(j = 1000000; j > 0; j--);
           LPC_GPIO0->FIOCLR = 0x00400000;
           comnd[2]='2';
           break;
        }
    }

    delayMs(0,500);
    

    /*for(j=0;j<4;j++){
    USB_WriteEP(CDC_DEP_IN, (unsigned char *)&comnd[0], hu);
    delayMs(0,1000);
    }

if((res = f_open(&File, "data.txt", FA_OPEN_EXISTING | FA_READ | FA_WRITE)) == 0){
    fpp = &File ;
    //res = f_read(&File, buffer, sizeof(buffer), &br);
    res = f_lseek(&File, fpp->fsize);
    while(1){
        for(j=0;j<2;j++){
        MuxOp(comnd[j]);
        sprintf(Float_STR,"%3.2f\r\n",adc);
        res = f_write(&File,Float_STR,(BYTE)strlen(Float_STR),&btw);
        delayMs(0,5) ;
    }
    //print new line
    }
    res = f_close(&File);
    }*/


}

after the adc initialization, device not enumerates in pc side !!!

I only use adc polling. What could be the mistake ? Do I need to re enable interrupts? I need to write adc readings to sd card. So can all ssp, usb and adc be executed same time ??

Thank You

Re: Lpc1769 ADC+USB+SSP

lpcware — Thu, 16 Jun 2016 02:26:44 GMT

Content originally posted in LPCWare by Ex-Zero on Fri Jun 22 05:26:21 MST 2012
What's your P1.30 :confused: VBUS or AD0.4 ?

Re: Lpc1769 ADC+USB+SSP

lpcware — Thu, 16 Jun 2016 02:26:44 GMT

Content originally posted in LPCWare by ranaya on Fri Jun 22 09:27:35 MST 2012
Thank you Mr.Hero :)

Yes that was the silly mistake. User manual helped me to configure the IO. Btw can u tell me what would be the effect of USB, adc and ssp interrupts if executed same time ?

Thank You

Re: Lpc1769 ADC+USB+SSP

lpcware — Thu, 16 Jun 2016 02:26:45 GMT

Content originally posted in LPCWare by Ex-Zero on Fri Jun 22 11:40:45 MST 2012

Quote: ranaya
... the effect of USB, adc and ssp interrupts if executed same time

If they have the same interrupt priority: Tail chaining

See: http://www.arm.com/files/pdf/IntroToCortex-M3.pdf

Quote:

The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced earlier by exerting higher [COLOR=Red]priority[/COLOR]. It also supports dynamic reprioritisation of interrupts. Priority levels can be changed by software during run time. Interrupts that are being serviced are blocked from further activation until the interrupt service routine is completed, so their priority can be changed without risk of accidental re-entry. In the case of back-to-back interrupts, traditional systems would repeat the complete state save and restore cycle twice, resulting in higher latency. The Cortex-M3 processor simplifies moving between active and pending interrupts by implementing[COLOR=Red] tail-chaining[/COLOR] technology in the NVIC hardware. Tailchaining achieves much lower latency by replacing serial stack pop and push actions that normally take over 30 clock cycles with a simple 6 cycle instruction fetch. The processor state is automatically saved on interrupt entry, and restored on interrupt exit, in fewer cycles than a software implementation, significantly enhancing performance in sub-100MHz systems.