topic Re: Interrupt enabling LPC1769 in LPCXpresso IDE

Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:12 GMT

Content originally posted in LPCWare by deBoogle on Thu Feb 17 14:37:02 MST 2011
Hi Guys,

I am a little confused about Interrupt enabling. The user manual suggests that there are two enable registers, ISER0 and ISER1. The only reference I have found to these so far is by doing,

NVIC->ISER, there seems to be no way of specifying ISER0 or ISER1, is there a struct defined for the ISER registers?

for example I wish to enable bit 29 to turn enable RIT interrupt.

I have seem some references on this forum to function calls to enable ie,

void IRQ_enable (...)

Is there a header file that allows me to set using function calls???

Can anyone set me straight?

Thanks in advance.
deBoogle

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:13 GMT

Content originally posted in LPCWare by deBoogle on Fri Feb 18 00:38:46 MST 2011
Thanks for the fast response,

the confusion for me was simply the naming, for example nearly all the other registers I have seen so far following the naming given in the datasheet. ie SysCon = SC= LPC_SC, GPIO = LPC_GPIO2 etc. The ISER registers as you have stated aren't named so. But hey that's a small issue. I was looking for an NVIC struct thats all.

Funnily enough I have just started making a note of which include files do what, and where to find stuff.

I love his chip but the learning curve is steep.

deBoogle

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:14 GMT

Content originally posted in LPCWare by TheFallGuy on Fri Feb 18 01:16:44 MST 2011
I think the naming is different because the NVIC is a generic Cortex-M3 peripheral (i.e. available on all Cortex-M3s from all vendors), whereas the peripherals named LPC* are specific to NXP.

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:14 GMT

Content originally posted in LPCWare by deBoogle on Fri Feb 18 01:54:48 MST 2011
That would certainly explain it. :)

deBoogle

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:15 GMT

Content originally posted in LPCWare by deBoogle on Fri Feb 18 02:20:04 MST 2011
To anybody else reading in the future if you are going to use the suggestion below:

NVIC_ENABLE0 = NVIC_ENABLE0 | (1<<29);

You must make sure that the CortexM3.h is included in your project!!

Probably obvious to y'all but I spent 20mins wondering why i was getting an error as I thought this was included by default in all the crazy setup files for the cortex...

deBoogle

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:15 GMT

Content originally posted in LPCWare by Ex-Zero on Fri Feb 18 04:46:30 MST 2011
If you include LPC17xx.h, core_cm3.h is included there.

If you use CMSIS (Start open new project with 'LPCXpresso C Project') this is done by default.

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:16 GMT

Content originally posted in LPCWare by acavaleiro on Thu May 19 18:08:27 MST 2011
Resuming:

    //enable the Interrupt vector
    NVIC_EnableIRQ(RIT_IRQn);          //must #include core_cm3.h , #include LPC17xx.h and cr_startup_lpc17.h

    //handling the interrupt vector
    void RIT_IRQHandler(void)
    {
            //do something
    }

That's all.
Try to use the F3 key to get the declarations and try to use the tool from NXP. They have alaready donne the hard job (drivers for all modules).
You have all the drivers to all devices on the microcontroller....

I have worked with Atmel for 2 years and this LPC micros and the NXP tool are really good and fast to understand...you just need to read the datasheet, use the NXP tools and drivers and do some tests..."et voilá"!

Good work

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:17 GMT

Content originally posted in LPCWare by Artay on Mon Jul 18 06:57:06 MST 2011
Hello all,

I thought I would continue in this thread rather than starting a new one. I am confused about Interrupt enable/disable as well.
My problem seems to be that interrupt is enabled and disabled at the same time, which sounds impossible
Here is the relevant part of my code:

NVIC_EnableIRQ(1);
// NVIC_EnableIRQ(TIMER0_IRQn);
(I commented out the bottom one just to try an alternative, but obviously they produce the same result.)
Now when I look up the NVIC register during debugging, that statement causes both the SETENA0 and CLRENA0 registers to go to 0x00000002 and 0x00000002.
I am assuming SETENA0 and CLRENA0 stand for Interrupt Set-Enable Register 0 and Interrupt Clear-Enable Register 0 registers, which seem to be for enabling and disabling the peripheral interrupts respectively. So I'm completely confused about how those two registers can be set by the same statement.

Many thanks for any insight into this.

**************************
**************************
**************************

OH never mind. Actually 1 on the interrupt clear-enable register indicates that the particular interrupt is enabled. 0 would have indicated the interrupt is disabled. So yes, the two registers are supposed to match. Sorry if that took up anybody's time and thanks.

*************************
*************************
*************************

Just in case somebody experiences the same problem, the reason I ended up going through the process of looking at the registers is because my timer didn't seem to initialize properly. As it turns out, that happened because after resetting the timer control register (TCR), I did not release the reset. As the manual (which has a typo) says, The counters remain reset until TCR[1] is returned to zero. So this is the sequence that seems to be needed:

LPC_TIM0->TCR |= 1 << 1;              // Reset Timer0
                                                           // timer control register (TCR) bit 1 (Counter Reset), bit
LPC_TIM0->TCR &= ~(1<<1);                 // release reset *IMPORTANT*
NVIC_EnableIRQ(1);
//NVIC_EnableIRQ(TIMER0_IRQn);          // Enable timer interrupt
                                                                    // this is in core_cm3.h
                                                                    // the path to it is thru lpc17xx_nvic.c --> lpc17xx.h --> core_cm3.h
LPC_TIM0->TCR |= 1 << 0;                     // Start timer
                                                                   // timer control register (TCT) bit 0(Counter Enable)

At least that's how it worked for me.

Re: Interrupt enabling LPC1769

lpcware — Thu, 16 Jun 2016 02:25:18 GMT

Content originally posted in LPCWare by Rob65 on Mon Jul 18 12:57:10 MST 2011

Quote: Artay

I am assuming SETENA0 and CLRENA0 stand for Interrupt Set-Enable Register 0 and Interrupt Clear-Enable Register 0 registers, which seem to be for enabling and disabling the peripheral interrupts respectively.

Never ever assume anything ...
Always check the User Manual even if you think you know what a register means ...
I am using lpc1xxx/2xxx chips for more than 5 years but I still check the user manual when programming a peripheral.

And there is a reason for the examples to be included with the LPCXpresso distributions and that's simply because they are so darn usefull to learn how to use a peripheral :eek:

Regards, Rob