topic Re: LPC1343 UART Tx FIFO level in LPCXpresso IDE

LPC1343 UART Tx FIFO level

lpcware — Thu, 16 Jun 2016 02:54:26 GMT

Content originally posted in LPCWare by simonbr on Thu Mar 25 02:04:53 MST 2010
Hi,

I want to use the U0FIFOLVL register to see how many characters can still be loaded into the Tx FIFO. But for some reason this does not work.

The relevant piece of code in my "putcom" routine is:

if ((LPC_UART->FIFOLVL&0xF00)!=0xF00) // any space left in FIFO?
{[INDENT]   LPC_UART->THR = databyte;       // write the character
[/INDENT]}
else
{[INDENT]   (...)
[/INDENT]}

What I'm seeing is that the condition never becomes false (a breakpoint in the "else" part never triggers), while after 16 characters the next character is transmitted corrupted; apparently the FIFO is overwritten when full.
I also tried with

if ((LPC_UART->FIFOLVL&0xF00)!=0x800)

but that did not make a difference.

I'm wondering what mistake I made, or whether the FIFOLVL register actually does not show the Tx FIFO level correctly.

Best regards,
Simon Brouwer

Re: LPC1343 UART Tx FIFO level

lpcware — Thu, 16 Jun 2016 02:54:26 GMT

Content originally posted in LPCWare by simonbr on Fri Mar 26 15:10:30 MST 2010
I have made the attached small program, just to illustrate the problem. Using an oscilloscope, I verified actual transmission on 9600 baud. The program writes data into the UART much faster, so the FIFOLVL register should become nonzero, but [B]it never does[/B].

I conclude that the FIFOLVL register [B]does not work[/B] as advertised.

Prove me wrong if you can!!!

Re: LPC1343 UART Tx FIFO level

lpcware — Thu, 16 Jun 2016 02:54:27 GMT

Content originally posted in LPCWare by zoks on Sun Jun 20 09:13:50 MST 2010
I have the same problem on LPC1768. UxFIFOLVL always reads 0. Is there anything else to do to get it working except enabling FIFO's?

If FIFO level can't be read then I guess using THRE is the only option, which effectively means sending byte by byte once the FIFO gets filled-up, making it useless for anything more than 16 bytes?

Re: LPC1343 UART Tx FIFO level

lpcware — Thu, 16 Jun 2016 02:54:28 GMT

Content originally posted in LPCWare by rkiryanov on Sun Jun 20 11:04:17 MST 2010
User manual, Revision history:
U0FIFOLVL register removed in Chapter 11.

There is no U0FIFOLVL in the LPC13xx.

Re: LPC1343 UART Tx FIFO level

lpcware — Thu, 16 Jun 2016 02:54:28 GMT

Content originally posted in LPCWare by rkiryanov on Sun Jun 20 11:06:43 MST 2010
LPCxxxx UARTs are undistinguished.

Re: LPC1343 UART Tx FIFO level

lpcware — Thu, 16 Jun 2016 02:54:29 GMT

Content originally posted in LPCWare by callendorph on Wed Jul 07 17:31:58 MST 2010
Can you point me to where that is documented on the user manuals for the LPC17xx and LPC13xx? The user manual on NXP's website for both series of processors still list the FIFOLVL register and the revision history doesn't say anything about removing it. Also, the errata documents don't say anything about that register being dropped from the specification. Anybody found a resolution to this?

Latest User Manual For LPC17xx on NXP website
http://www.nxp.com/documents/user_manual/UM10360.pdf

Re: LPC1343 UART Tx FIFO level

lpcware — Thu, 16 Jun 2016 02:54:30 GMT

Content originally posted in LPCWare by rkiryanov on Wed Jul 07 21:10:58 MST 2010

Quote: callendorph
Can you point me to where that is documented on the user manuals for the LPC17xx and LPC13xx?

13xx
http://ics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc13xx.pdf