LPCXpresso IDE中的主题 Re: Understanding the Cortex-M3 (LPC1769) interrupt model.

Understanding the Cortex-M3 (LPC1769) interrupt model.

lpcware — Wed, 15 Jun 2016 23:46:43 GMT

Content originally posted in LPCWare by skysat on Sat Jan 18 10:33:40 MST 2014
I'm having trouble understanding exactly how interrupts/exceptions work on the M3. To my way of thinking, an interrupt works like this:

1. Push the PSR (which includes the interrupt enable bit).
2. Push the PC.
3. Disable interrupts.
4. Execute the ISR.

The ISR may or may not re-enable interrupts but upon exit, the former PSR will be restored thus restoring the former interrupt enable/disable state. The following code is at the end of my ISR:

213       }
0000c0d0:   add.w   r7, r7, #24
0000c0d4:   mov     sp, r7
0000c0d6:   pop     {r7, pc}
0000c0d8:   adds    r5, r7, #4
0000c0da:   asrs    r0, r0, #32

(Are the last two instructions filler or data? I notice that "Show Opcodes" doesn't do anything.)
The debugger seems to think that I have a PSR (although it doesn't know what the bits mean).   Where is the PSR documented. I don't see any interrupts being enabled.

So, are interrupts globally disabled? Is the particular interrupt disabled? Can someone explain EXACTLY what is going on?

You would think that the answer to these questions would be in the "Cortex-M3 Technical Reference Manual" (there is a puny chapter on the NVIC).

Randy

An then there is the matter of return address 0xfffffff8. I'll handle that in my next post - "Where's my stack?".

Re: Understanding the Cortex-M3 (LPC1769) interrupt model.

lpcware — Wed, 15 Jun 2016 23:46:44 GMT

Content originally posted in LPCWare by TheFallGuy on Sat Jan 18 11:15:54 MST 2014
A good place to start is to read the "Definitive Guide to the Cortex-M3" by Joseph Yui.

Failing, that, there is a lot of technical documentation on the ARM Website.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABDGADF.html

There are chapters on the programmers model, Exceptions and Interrupts and the Stack.

Re: Understanding the Cortex-M3 (LPC1769) interrupt model.

lpcware — Wed, 15 Jun 2016 23:46:44 GMT

Content originally posted in LPCWare by skysat on Sat Jan 18 13:27:29 MST 2014
Thanks to some gentle prodding by TheFallGuy, I can answer my own questions.

1. What are those final two instructions?
    OK, I can't answer that one but they still look like filler to me.

2. So, are interrupts globally disabled?
    No.

3. Is the particular interrupt disabled?
    Yes, the IRQ that caused execution of the ISR is disabled until the ISR returns.

4. Can someone explain EXACTLY what is going on?
    Yes, his name is Joseph Yiu.

Re: Understanding the Cortex-M3 (LPC1769) interrupt model.

lpcware — Wed, 15 Jun 2016 23:46:45 GMT

Content originally posted in LPCWare by TheFallGuy on Sun Jan 19 03:27:29 MST 2014
1. Not filler - constants. 16-bit Thumb instructions set do not allow loading of large constant values, so they are often loaded by using PC-relative addressing. These constants are normally placed at the end of a function. This is what you are seeing.