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    <title>LPCXpresso IDE中的主题 LPC1769, ADC with NXP CMSIS</title>
    <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC1769-ADC-with-NXP-CMSIS/m-p/566008#M18256</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by JojoS on Sun Mar 11 08:50:19 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm playing with the LPCXpresso and have used the webserver RTOSDemo_RDB1768. I have modified the sources to use the ADC with interrups. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Somehow it worked, but the converson rate did not match my setting in ADC_init(); I found there is a problem with setting a low sampling rate: then the divider becomes &amp;gt;255 and writes in other control bits than the estimated divider bits. The cmsis driver should check this, is there any address to report such problems?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I found also that there is a newer driver lib availible at NXP with improved clock setting. It takes into account that a conversion takes 65 clocks. But there was another little bug: the init function reads the cpu clock:&lt;/SPAN&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;ADCPClk = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_ADC);&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;SPAN&gt;In my case I used some (none cmsis) code to change the clock to 120 MHz, but the GetPCLK returned 100 MHz. After adding a ClockUpdate it worked fine:&lt;/SPAN&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;
 
SystemCoreClockUpdate();
 
 
ADCPClk = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_ADC);
&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;SPAN&gt;Maybe it is better to include the clock update function in the GetPCLK() to make sure to use the correct clock? I guess there are other places in the code where this can lead to wrong clock settings. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;And another question: I found the updated CMSIS driver lib at NXP, but now I replaced only the adc code. I was not successful to create a new project in the Code Red IDE that creates a whole new CMSIS 2.0+drivers lib. Can anyone describe the necessary steps to create this project? In the NXP download are no project files for the CR environment.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 16 Jun 2016 02:17:29 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-16T02:17:29Z</dc:date>
    <item>
      <title>LPC1769, ADC with NXP CMSIS</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC1769-ADC-with-NXP-CMSIS/m-p/566008#M18256</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by JojoS on Sun Mar 11 08:50:19 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm playing with the LPCXpresso and have used the webserver RTOSDemo_RDB1768. I have modified the sources to use the ADC with interrups. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Somehow it worked, but the converson rate did not match my setting in ADC_init(); I found there is a problem with setting a low sampling rate: then the divider becomes &amp;gt;255 and writes in other control bits than the estimated divider bits. The cmsis driver should check this, is there any address to report such problems?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I found also that there is a newer driver lib availible at NXP with improved clock setting. It takes into account that a conversion takes 65 clocks. But there was another little bug: the init function reads the cpu clock:&lt;/SPAN&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;ADCPClk = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_ADC);&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;SPAN&gt;In my case I used some (none cmsis) code to change the clock to 120 MHz, but the GetPCLK returned 100 MHz. After adding a ClockUpdate it worked fine:&lt;/SPAN&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;
 
SystemCoreClockUpdate();
 
 
ADCPClk = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_ADC);
&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;SPAN&gt;Maybe it is better to include the clock update function in the GetPCLK() to make sure to use the correct clock? I guess there are other places in the code where this can lead to wrong clock settings. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;And another question: I found the updated CMSIS driver lib at NXP, but now I replaced only the adc code. I was not successful to create a new project in the Code Red IDE that creates a whole new CMSIS 2.0+drivers lib. Can anyone describe the necessary steps to create this project? In the NXP download are no project files for the CR environment.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Jun 2016 02:17:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/LPC1769-ADC-with-NXP-CMSIS/m-p/566008#M18256</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-16T02:17:29Z</dc:date>
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