LPC 1343 - problem with UART and frequency

lpcware — Thu, 16 Jun 2016 02:14:46 GMT

Content originally posted in LPCWare by lsbach_plum on Mon Mar 12 04:44:47 MST 2012
Hi,
I have a problem with setting the frequency for the UART. I have PLL set to get 24 MHz (M = 0, P = 4). Ultimately, I want to get 115200. And then there is a problem. I receive bad data sent by the computer.

code PLL:
    //PLL - 24MHz
    LPC_SYSCON->SYSPLLCTRL &= ~(0x1F);
    LPC_SYSCON->SYSPLLCTRL |= 0x01;            //M = 0 + 1

    LPC_SYSCON->SYSPLLCTRL &= ~(0x60);        //P = 1
    LPC_SYSCON->SYSPLLCTRL |= (1 << 6);        //6//P = 4

    LPC_SYSCON->PDRUNCFG &= ~(1 << 7);            //System PLL powered
    while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));   //Wait Until PLL Locked

code UART Init:
    uint32_t Fdiv = 0x00;
    uint32_t regVal = 0x00;

    UARTCount = 0;

    NVIC_DisableIRQ(UART_IRQn);                // deaktywacja przerwań dla UART

    // UART wej/wyj konfiguracja
    LPC_IOCON->PIO1_6 &= ~0x07;
    LPC_IOCON->PIO1_6 |= 0x01;                // UART RxD
    LPC_IOCON->PIO1_7 &= ~0x07;
    LPC_IOCON->PIO1_7 |= 0x01;                // UART TxD

    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);    //wlaczenie zasilania kontrolera UART
    LPC_SYSCON->UARTCLKDIV = 0x01;            //wlaczenie zegara poprzez ustawienie preskalera(ustawia 1)

    LPC_UART->LCR |= 0x83;                    // utawienie: 8b danych, brak parzystosci, 1b stopu
    regVal = (LPC_SYSCON->UARTCLKDIV) & 0xFF;

    //Fdiv = (((SYSTEM_CORE_CLOCK * LPC_SYSCON->SYSAHBCLKDIV) / regVal) / 16) / baudrate;        //baudrate

    LPC_UART->DLM = Fdiv / 256;
    LPC_UART->DLL = Fdiv % 256;
    LPC_UART->LCR = 0x03;            // wyłączenie dostepu do rejestrów Divisor Latches(DLAB=0)
    LPC_UART->FCR = 0x07;            // włączenie kolejek TX i RX

    // odczytanie i zapisanie statusu linii
    regVal = (LPC_UART->LSR) & 0xFF;

    while ((LPC_UART->LSR & (LSR_THRE | LSR_TEMT)) != (LSR_THRE | LSR_TEMT));
    while (LPC_UART->LSR & LSR_RDR)
    {
        regVal = LPC_UART->RBR;
    }

    // włączenie przerwań od UART
    NVIC_EnableIRQ(UART_IRQn);
    LPC_UART->IER = IER_RBR | IER_THRE ;

    return;

where
      SYSTEM_CORE_CLOCK = 24 000 000
      SYSAHBCLKDIV = 1.

when I used the default settings (PLL increases to 72MHz) is working properly.

Where I make mistake?

Re: LPC 1343 - problem with UART and frequency

lpcware — Thu, 16 Jun 2016 02:14:48 GMT

Content originally posted in LPCWare by gbm on Mon Mar 12 05:39:25 MST 2012
I can't see in your code the sequence switching to PLL clock. You are still running from 12 MHz IRC.

topic Re: LPC 1343 - problem with UART and frequency in LPCXpresso IDE

LPC 1343 - problem with UART and frequency

Re: LPC 1343 - problem with UART and frequency