topic Re: systic example / PCXpresso LPC1343 Examples V1.10 in LPCXpresso IDE

systic example / PCXpresso LPC1343 Examples V1.10

lpcware — Thu, 16 Jun 2016 00:54:47 GMT

Content originally posted in LPCWare by pawel on Thu Jan 21 15:31:33 MST 2010
Hi All,

I am trying to analyze examples for LPC1343.
Register bit 2 in System Timer Control and status register is defined and used in samples but in manual (UM10375_1; Rev. 01.01 — 11 January 2010) I can find only information that this bit is reserved.
Am I missed something? When can we expect production ready manual (not draft, without <tbd>)?

- Pawel

/* SysTick Control / Status Register Definitions */
{...}
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

Re: systic example / PCXpresso LPC1343 Examples V1.10

lpcware — Thu, 16 Jun 2016 00:54:48 GMT

Content originally posted in LPCWare by igorsk on Thu Jan 21 16:02:40 MST 2010
As SysTick is (supposed to be) standard to all Cortex-M3 implementations, the registers are also described in the ARMv7-M Architecture Reference Manual (DDI0403 or DDI0405), as well as in Cortex-M3 TRM (DDI0337). The latter descibes the register thus:

[31:17]
Reserved.

[16] COUNTFLAG
Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.

[2] CLKSOURCE
0 = external reference clock.
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are Unpredictable.

[1] TICKINT
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0.

[0] ENABLE
1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting.
0 = counter disabled.

Re: systic example / PCXpresso LPC1343 Examples V1.10

lpcware — Thu, 16 Jun 2016 00:54:48 GMT

Content originally posted in LPCWare by pawel on Thu Jan 21 17:03:22 MST 2010
Thank you igorsk,

So in systick_main.c I can find something like this:

if ( !(SysTick->CTRL & (1<<SysTick_CTRL_CLKSOURCE_Msk)) )
{
/* When external reference clock is used(CLKSOURCE in
Systick Control and register bit 2 is set to 0), the
SYSTICKCLKDIV must be a non-zero value and 2.5 times
faster than the reference clock.
When core clock, or system AHB clock, is used(CLKSOURCE
in Systick Control and register bit 2 is set to 1), the
SYSTICKCLKDIV has no effect to the SYSTICK frequency. See
more on Systick clock and status register in Cortex-M3
technical Reference Manual. */
LPC_SYSCON->SYSTICKCLKDIV = 0x08;
}

And first line should be:

if ( !(SysTick->CTRL & (1<<SysTick_CTRL_CLKSOURCE_Pos)) )

or

if ( !(SysTick->CTRL & (SysTick_CTRL_CLKSOURCE_Msk)) )

- Pawel

Re: systic example / PCXpresso LPC1343 Examples V1.10

lpcware — Thu, 16 Jun 2016 00:54:49 GMT

Content originally posted in LPCWare by NXP_USA on Mon Jan 25 00:05:25 MST 2010

Quote: pawel
Thank you igorsk,

So in systick_main.c I can find something like this:

if ( !(SysTick->CTRL & (1<<SysTick_CTRL_CLKSOURCE_Msk)) )
{

[...]
And first line should be:

if ( !(SysTick->CTRL & (1<<SysTick_CTRL_CLKSOURCE_Pos)) )

or

if ( !(SysTick->CTRL & (SysTick_CTRL_CLKSOURCE_Msk)) )

- Pawel

Hi Pawel,

Thank you for noticing this error. The code has been changed to

if ( !(SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) )

It will be released in the next example bundle update.

-NXP