topic Re: M0 inline assembly: subs r0, #32 not supported in LPCXpresso IDE

M0 inline assembly: subs r0, #32 not supported

lpcware — Thu, 16 Jun 2016 02:16:47 GMT

Content originally posted in LPCWare by rkiryanov on Tue Apr 27 09:02:12 MST 2010
What am I doing wrong?

Quote:
Building file: ../src/OS/os_kernel.cpp
Invoking: MCU C++ Compiler
arm-none-eabi-c++ -DNDEBUG -D__CODE_RED -O3 -Os -g -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -Wa,-ahlnds=os_kernel.asm -mcpu=cortex-m0 -mthumb -D__NEWLIB__ -MMD -MP -MF"src/OS/os_kernel.d" -MT"src/OS/os_kernel.d" -o"src/OS/os_kernel.o" "../src/OS/os_kernel.cpp"
C:\DOCUME~1\user\LOCALS~1\Temp\ccs4Wgyb.s: Assembler messages:
C:\DOCUME~1\user\LOCALS~1\Temp\ccs4Wgyb.s:3676: Error: instruction not supported in Thumb16 mode -- `subs r0,#32'
C:\DOCUME~1\user\LOCALS~1\Temp\ccs4Wgyb.s:3683: Error: instruction not supported in Thumb16 mode -- `subs r0,#32'

DDI0419B_arm_architecture_v6m_reference_manual_errata_markup_2_0.pdf

Quote:
A6.7.65 SUB (immediate)
This instruction subtracts an immediate value from a register value, and writes the result to the destination register. The condition flags are updated based on the result.

Encoding T2 All versions of the Thumb ISA.
SUBS <Rdn>,#<imm8>

Re: M0 inline assembly: subs r0, #32 not supported

lpcware — Thu, 16 Jun 2016 02:16:48 GMT

Content originally posted in LPCWare by CodeRedSupport on Tue Apr 27 09:32:44 MST 2010
This works for me....

void test(unsigned int a, unsigned int b)
{
asm(".syntax unified");
asm("subs r0, #32;");
asm(".syntax divided");
}

I suspect you might be missing the .syntax directives.

Regards,
CodeRedSupport.

Re: M0 inline assembly: subs r0, #32 not supported

lpcware — Thu, 16 Jun 2016 02:16:49 GMT

Content originally posted in LPCWare by rkiryanov on Wed Apr 28 06:43:34 MST 2010
Thanks!

How can I determine, what is core selected? I want to use Cortex-M3 instructions if possible.

#if (__CORE__ == __ARM7M__) // IAR
// code for ARMv7-M: it, stmdb, ldmia, clz
#else
// code for ARMv6-M: beq, mov, mov, mov, stm, mov, subs
#endif

Re: M0 inline assembly: subs r0, #32 not supported

lpcware — Thu, 16 Jun 2016 02:16:49 GMT

Content originally posted in LPCWare by CodeRedSupport on Wed Apr 28 07:32:12 MST 2010
When you compile for LPC11xx (cortex-m0), the compiler will automatically set the following define:

#define __ARM_ARCH_6M__ 1

When you compile for LPC13xx/LCP17xx (cortex-m3), the compiler will automatically set the following define:

#define __ARM_ARCH_7M__ 1

You should be able to use these defines to conditionally include the appropriate code for your target.

To see all the defines generated by the compiler, Ctrl-click on the project name in the bottom right of the status bar of the LPCXpresso IDE to open a command prompt with the compiler tools set up on the path. Then enter:

arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -E -dD -

After pressing Enter, press Ctrl-Z and Enter again. The list of defines will be displayed on screen. [Note - change the processor to cortex-m0 if you are interested in LPC11 rather than LPC13/17.]

Regards
CodeRedSupport