topic Re: LPC1102 Sleep Issues in LPCXpresso IDE

LPC1102 Sleep Issues

lpcware — Wed, 15 Jun 2016 22:19:36 GMT

Content originally posted in LPCWare by epalmer22 on Tue Aug 23 08:45:32 MST 2011
Has anyone been able to get the LPC1102 in to Sleep Mode? The User Manual states to clear the DPDEN bit by writing to the DPDFLAG in the PCON register (Page 29 of UM10429). The problem is, there is no DPDEN or DPDFLAG in the PCON register. However, I found that these bits are in the LPC1114 User Manual (UM10398).

Thanks.

Re: LPC1102 Sleep Issues

lpcware — Wed, 15 Jun 2016 22:19:37 GMT

Content originally posted in LPCWare by kendwyer on Tue Aug 23 23:43:29 MST 2011
This device does not support Deep Power Down mode. The Datasheet states:
[I]
Two reduced power modes: Sleep and Deep-sleep modes

[/I]Reason that this mode is not available is because the part does not have a Wake-Up pin

Re: LPC1102 Sleep Issues

lpcware — Wed, 15 Jun 2016 22:19:38 GMT

Content originally posted in LPCWare by serge on Tue Aug 23 23:54:28 MST 2011
Bit 8 of the PCON register is the SLEEPFLAG.
Other bits of this register are reserved and have to be 0x0

For more info read the user manual UM10429 chapter 4.2.1

And indeed power control is a bit different from the LPC1114.

Are you building example code or your own software?

Re: LPC1102 Sleep Issues

lpcware — Wed, 15 Jun 2016 22:19:38 GMT

Content originally posted in LPCWare by epalmer22 on Wed Sep 28 08:40:16 MST 2011
Problem solved!!

Before entering Deep Sleep Mode, all I/O need to have their internal resistor disabled and they have to be set to outputs and driven low. This was resulting in a current draw of 50uA, far greater than the 1uA spec.

It turns out that there is are additional I/O in the M0 core that need to be considered, even though they are not brought out to the pins of the LPC1102. As per UM10398 (for LPC111x controllers), the I/O specified in this document also need to be written to (disable internal resistor and driven low) to get the current down to the spec. I acheived a Deep Sleep Mode current draw of 2uA. This is not reflected in the LPC1102 User Manual (UM10429), but should be added.

Re: LPC1102 Sleep Issues

lpcware — Wed, 15 Jun 2016 22:19:39 GMT

Content originally posted in LPCWare by kendwyer on Thu Sep 29 07:50:59 MST 2011
This is mentioned in the DS:

Deep-sleep mode; VDD = 3.3 V [2][3][8] 2uA

[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

Re: LPC1102 Sleep Issues

lpcware — Wed, 15 Jun 2016 22:19:40 GMT

Content originally posted in LPCWare by epalmer22 on Thu Nov 17 08:59:21 MST 2011
Ken, That is correct, but I am referring to is I/O that is NOT brought out to pins on the LPC1102. For example, the I/O that the LPC1114 contains still needs to be written to, when using the LPC1102, to get down to 2uA.