topic Re: Interrupt levels in LPC11xx in LPCXpresso IDE

Interrupt levels in LPC11xx

lpcware — Thu, 16 Jun 2016 02:16:23 GMT

Content originally posted in LPCWare by ArtjomGromak on Wed Mar 14 08:48:59 MST 2012
Hi!
LPC11xx have 4 levels of interrupt.
How I can disable all interrupt of given level: for exsample disable/ enable interrupt of level 3 or 2. It is possible?
Thanks.

Re: Interrupt levels in LPC11xx

lpcware — Thu, 16 Jun 2016 02:16:24 GMT

Content originally posted in LPCWare by Ex-Zero on Wed Mar 14 09:10:40 MST 2012

Quote: ArtjomGromak
How I can disable all interrupt of given level: for exsample disable/ enable interrupt of level 3 or 2. It is possible?

Yes, write a function to read Interrupt Priority Registers and disable / enable all interrupts with appropriate value :rolleyes:

Re: Interrupt levels in LPC11xx

lpcware — Thu, 16 Jun 2016 02:16:25 GMT

Content originally posted in LPCWare by ArtjomGromak on Wed Mar 14 10:29:16 MST 2012
That is you suggest to write to 8 registers(IP0-IP7)?
It requires long time.

I meant such possibility: for example, I will take the xmega processor (not ARM). Xmega have 3 interrupt levels. To disable level I must write to 1 register:

PMIC.CTRL&=(1<<LOLVLEN); // disable lowest priority level
PMIC.CTRL|=(1<<HILVLEN)|(1<<MEDLVLEN); // enable high and medium level

It is executed 4-5 commands.
Whether there is in Cortex-M0 something similar?

Re: Interrupt levels in LPC11xx

lpcware — Thu, 16 Jun 2016 02:16:25 GMT

Content originally posted in LPCWare by Ex-Zero on Wed Mar 14 10:37:50 MST 2012

Quote: ArtjomGromak
I meant such possibility...

I know :rolleyes:

If there would be such an option I wouldn't have suggested to read Priority Registers :)

So the answer is still: there's no register or command to group enable/disable interrupts :(

Re: Interrupt levels in LPC11xx

lpcware — Thu, 16 Jun 2016 02:16:26 GMT

Content originally posted in LPCWare by ArtjomGromak on Thu Mar 15 06:00:37 MST 2012

Quote: Zero
I know :rolleyes:
So the answer is still: there's no register or command to group enable/disable interrupts :(

I see.
Thanks.

Re: Interrupt levels in LPC11xx

lpcware — Thu, 16 Jun 2016 02:16:27 GMT

Content originally posted in LPCWare by CodeRedSupport on Thu Mar 15 07:43:21 MST 2012
FYI - You can do this on Cortex-M3 based parts like LPC13 and LPC17 using the NVIC's BASEPRI register, but not on Cortex-M0 based parts like LPC11 (which don't have this register implemented in their NVIC).

Regards,
CodeRedSupport