LPCXpresso IDEのトピックRe: SPI LPCXpresso example code

SPI LPCXpresso example code

lpcware — Wed, 15 Jun 2016 23:39:11 GMT

Content originally posted in LPCWare by tyassin on Thu Aug 22 05:50:30 MST 2013
Hi,

I just have a question about this piece of code from the SPI example for the LPC1114.

void SSP_Init( void )
{
 uint8_t i, Dummy=Dummy;

 /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
 LPC_SSP0->CR0 = 0x0707;

 /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */
 LPC_SSP0->CPSR = 16;

 for ( i = 0; i < FIFOSIZE; i++ )
 {
   Dummy = LPC_SSP0->DR;/* clear the RxFIFO */
 }

 /* Enable the SSP Interrupt */
 //NVIC_EnableIRQ(SSP0_IRQn);

 /* Device select as master, SSP Enabled */
 #if SSP_SLAVE
 /* Slave mode */
 if ( LPC_SSP0->CR1 & SSPCR1_SSE )
 {
   /* The slave bit can't be set until SSE bit is zero. */
   LPC_SSP0->CR1 &= ~SSPCR1_SSE;
 }
 LPC_SSP0->CR1 = SSPCR1_MS;/* Enable slave bit first */
 LPC_SSP0->CR1 |= SSPCR1_SSE;/* Enable SSP */
 #else
 /* Master mode */
 LPC_SSP0->CR1 = SSPCR1_SSE;
 #endif
 /* Set SSPINMS registers to enable interrupts */
 /* enable all error related interrupts */
 LPC_SSP0->IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM;

}

The bit I wonder about is why is it necessary to clear the FIFO at startup??

for ( i = 0; i < FIFOSIZE; i++ )
 {
   Dummy = LPC_SSP0->DR;/* clear the RxFIFO */
 }

Thank you

Re: SPI LPCXpresso example code

lpcware — Wed, 15 Jun 2016 23:39:12 GMT

Content originally posted in LPCWare by graynomad on Thu Aug 22 16:45:50 MST 2013
I don't know if it's strictly necessary with this hardware, I would assume (maybe incorrectly) that all appropriate registers and counters are zeroed at reset, but it's probably good practice and doesn't do any harm.

_____
Rob

Re: SPI LPCXpresso example code

lpcware — Wed, 15 Jun 2016 23:39:13 GMT

Content originally posted in LPCWare by embd02161991 on Thu Aug 22 22:48:00 MST 2013
Hi,

Whenever there is data in the Rx FIFO , the software would set RNE to 1 and this data would be read. This data would not be your required data .During this period any incoming data will be lost. In order to avoid this situation , the receiver FIFO is initially cleared before enabling the interrupts.

Thanks,
KS

Re: SPI LPCXpresso example code

lpcware — Wed, 15 Jun 2016 23:39:13 GMT

Content originally posted in LPCWare by tyassin on Fri Aug 23 05:35:19 MST 2013
OK I understand, but why is it cleared in the for-loop, times x FIFO size? Is it not only one register?