topic WDT clock settings in LPCXpresso IDE https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561203#M16221 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by sallys21 on Tue Mar 12 09:51:55 MST 2013</STRONG><BR /><SPAN>I'm thoroughly going through my clock setup, since I seem to have issues with always having something wrong and putting my processor in a bad state <SPAN class="lia-unicode-emoji" title=":disappointed_face:"><LI-EMOJI id="lia_disappointed-face" title=":disappointed_face:"></LI-EMOJI></SPAN></SPAN><BR /><BR /><SPAN>Looking at my system_LPC11xx.c file, I noticed that the __WDT_OSC_CLK values don't match what's in the user manual...The __FREQSEL and __DIVSEL seem to be fine to calculate my clock value for the WDT, but the defines for the __WDT_OSC_CLK are different? I'm wondering if that's the reason why my guy keeps resetting and I'm not able to reprogram it?</SPAN><BR /><BR /><SPAN>I have my WDTOSCCTRL_Val = 0x180, so my FREQSEL(Fclkana) = 0xC, and DIVSEL = 0...wdt_osc_clk = 4Mhz/(2*(1+0)) = 2Mhz. But according to my system_LPC11xx.c file, my __WDT_OSC_CLK = 2900000/2 = 1.45Mhz</SPAN><BR /><BR /><SPAN><SPAN class="lia-unicode-emoji" title=":disappointed_face:"><LI-EMOJI id="lia_disappointed-face" title=":disappointed_face:"></LI-EMOJI></SPAN></SPAN><BR /><BR /><TABLE border="1"><TBODY><TR><TD bgcolor="#cacaca"> <PRE>#define __FREQSEL&nbsp;&nbsp; ((WDTOSCCTRL_Val &gt;&gt; 5) &amp; 0x0F) #define __DIVSEL&nbsp;&nbsp; (((WDTOSCCTRL_Val &amp; 0x1F) &lt;&lt; 1) + 2) #if (CLOCK_SETUP)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Clock Setup&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; */ &nbsp; #if (SYSCLK_SETUP)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* System Clock Setup&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; */ &nbsp;&nbsp;&nbsp; #if (WDTOSC_SETUP)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Watchdog Oscillator Setup*/ &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #if&nbsp; (__FREQSEL ==&nbsp; 0) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ( 400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 1) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ( 500000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 2) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ( 800000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 3) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1100000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 4) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 5) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1600000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 6) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1800000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 7) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2000000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 8) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2200000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 9) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 10) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2600000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 11) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2700000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 12) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2900000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 13) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3100000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 14) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3200000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #else &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #endif &nbsp;&nbsp;&nbsp; #else &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1600000 / 2) &nbsp;&nbsp;&nbsp; #endif&nbsp; // WDTOSC_SETUP</PRE> </TD></TR></TBODY></TABLE></BODY></HTML> Wed, 15 Jun 2016 23:39:02 GMT lpcware 2016-06-15T23:39:02Z WDT clock settings https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561203#M16221 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by sallys21 on Tue Mar 12 09:51:55 MST 2013</STRONG><BR /><SPAN>I'm thoroughly going through my clock setup, since I seem to have issues with always having something wrong and putting my processor in a bad state <SPAN class="lia-unicode-emoji" title=":disappointed_face:"><LI-EMOJI id="lia_disappointed-face" title=":disappointed_face:"></LI-EMOJI></SPAN></SPAN><BR /><BR /><SPAN>Looking at my system_LPC11xx.c file, I noticed that the __WDT_OSC_CLK values don't match what's in the user manual...The __FREQSEL and __DIVSEL seem to be fine to calculate my clock value for the WDT, but the defines for the __WDT_OSC_CLK are different? I'm wondering if that's the reason why my guy keeps resetting and I'm not able to reprogram it?</SPAN><BR /><BR /><SPAN>I have my WDTOSCCTRL_Val = 0x180, so my FREQSEL(Fclkana) = 0xC, and DIVSEL = 0...wdt_osc_clk = 4Mhz/(2*(1+0)) = 2Mhz. But according to my system_LPC11xx.c file, my __WDT_OSC_CLK = 2900000/2 = 1.45Mhz</SPAN><BR /><BR /><SPAN><SPAN class="lia-unicode-emoji" title=":disappointed_face:"><LI-EMOJI id="lia_disappointed-face" title=":disappointed_face:"></LI-EMOJI></SPAN></SPAN><BR /><BR /><TABLE border="1"><TBODY><TR><TD bgcolor="#cacaca"> <PRE>#define __FREQSEL&nbsp;&nbsp; ((WDTOSCCTRL_Val &gt;&gt; 5) &amp; 0x0F) #define __DIVSEL&nbsp;&nbsp; (((WDTOSCCTRL_Val &amp; 0x1F) &lt;&lt; 1) + 2) #if (CLOCK_SETUP)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Clock Setup&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; */ &nbsp; #if (SYSCLK_SETUP)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* System Clock Setup&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; */ &nbsp;&nbsp;&nbsp; #if (WDTOSC_SETUP)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Watchdog Oscillator Setup*/ &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #if&nbsp; (__FREQSEL ==&nbsp; 0) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ( 400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 1) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ( 500000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 2) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ( 800000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 3) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1100000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 4) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 5) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1600000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 6) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1800000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 7) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2000000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 8) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2200000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL ==&nbsp; 9) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 10) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2600000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 11) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2700000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 12) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2900000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 13) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3100000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #elif (__FREQSEL == 14) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3200000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #else &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3400000 / __DIVSEL) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #endif &nbsp;&nbsp;&nbsp; #else &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #define __WDT_OSC_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1600000 / 2) &nbsp;&nbsp;&nbsp; #endif&nbsp; // WDTOSC_SETUP</PRE> </TD></TR></TBODY></TABLE></BODY></HTML> Wed, 15 Jun 2016 23:39:02 GMT https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561203#M16221 lpcware 2016-06-15T23:39:02Z Re: WDT clock settings https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561204#M16222 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by Ex-Zero on Tue Mar 12 11:02:20 MST 2013</STRONG><BR /><SPAN>This is obviously a [COLOR=Red]LPC13xx[/COLOR] Fclkana table in CMSISv2p00_LPC11xx :eek::mad::eek:</SPAN><BR /><BR /><SPAN>Probably because no one expects this clock to be accurate (Datasheet: 'The frequency spread over processing and temperature is[COLOR=Red] +- 40 %[/COLOR]') :p</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:39:02 GMT https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561204#M16222 lpcware 2016-06-15T23:39:02Z Re: WDT clock settings https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561205#M16223 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by sallys21 on Tue Mar 12 11:16:06 MST 2013</STRONG><BR /><SPAN>Aha!</SPAN><BR /><BR /><SPAN>Makes sense.</SPAN><BR /><BR /><SPAN>Thanks Zero :D</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:39:03 GMT https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561205#M16223 lpcware 2016-06-15T23:39:03Z Re: WDT clock settings https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561206#M16224 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by Ex-Zero on Tue Mar 12 11:31:26 MST 2013</STRONG><BR /><SPAN>BTW: If you need a more accurate watchdog it's useful to use another timer and measure WDT clock ;)</SPAN><BR /><BR /><SPAN>There's a nice sample which is using this mechanism to time a wakeup (Sample 'timedwakeup' in NXP_LPCXpresso11C24_2011-01-27.zip) :)</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:39:04 GMT https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561206#M16224 lpcware 2016-06-15T23:39:04Z Re: WDT clock settings https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561207#M16225 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by sallys21 on Tue Mar 12 13:10:25 MST 2013</STRONG><BR /><SPAN>I planned on using the IRC for the clock source of the WDT...is this not accurate either?</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:39:04 GMT https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561207#M16225 lpcware 2016-06-15T23:39:04Z Re: WDT clock settings https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561208#M16226 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by Ex-Zero on Tue Mar 12 13:14:16 MST 2013</STRONG><BR /><SPAN>Datasheet :)</SPAN><BR /><BR /><HR /><SPAN style="color: #0000ff;"><STRONG>Quote: </STRONG><BR /><BR />7.16.1.1 Internal RC oscillator<BR />The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to [COLOR=Red]1 % accuracy[/COLOR] over the entire voltage and temperature range.</SPAN><HR /></BODY></HTML> Wed, 15 Jun 2016 23:39:05 GMT https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561208#M16226 lpcware 2016-06-15T23:39:05Z Re: WDT clock settings https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561209#M16227 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by sallys21 on Tue Mar 12 13:16:46 MST 2013</STRONG><BR /><SPAN>Okay, I thought you were going to bring something else up. :D</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:39:05 GMT https://community.nxp.com/t5/LPCXpresso-IDE/WDT-clock-settings/m-p/561209#M16227 lpcware 2016-06-15T23:39:05Z