Differences LPC1114 (Cortex-M0) / LPC1343 (Cortex-M3) / LPC1768 (Cortex-M3)...

lpcware — Thu, 16 Jun 2016 00:51:04 GMT

Content originally posted in LPCWare by capiman on Sat Jan 30 12:43:08 MST 2010
Hello,

has someone deeper knowledge about different nxp microcontrollers ?

I have successfully written programs for LPC1768, which is a Cortex-M3.
The peripheral looks like more or less copied from LPC2xxx family.

Now i have two LPCXpresso boards: one LPC1343 and one LPC1114.

Looking at the datasheet of LPC1343 it is also a Cortex-M3.
But the peripheral is completely different. E.g. the GPIO.
There are no more SET / CLR registers, instead you have a mechanism with address and value.

Now i started to compare the datasheet of LPC1343 with LPC1114.
The peripheral look to be similar to LPC1343.
Is it completely compatibel (at least for the components existing on both sides,
e.g. a gpio or uart, clocking for a component, power control for a component) ?

But then the LPC1114 is a Cortex-M0.
Is Cortex-M0 and Cortex-M3 binary compatible and only execution / internal handling is different ?

What i am also missing in nxp user manual:
In the LPC1768 user manual there was always a section "Basic configuration", e.g. for the UART0:

The UART0/2/3 peripherals are configured using the following registers:
1. Power: In the PCONP register (Table 4–46), set bits PCUART0/2/3.
Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled
(PCUART2/3 = 0).
2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_UART0; in the
PCLKSEL1 register (Table 4–41), select PCLK_UART2/3.
3. Baud rate: In register U0/2/3LCR (Table 14–278), set bit DLAB =1. This enables
access to registers DLL (Table 14–272) and DLM (Table 14–273) for setting the baud
rate. Also, if needed, set the fractional baud rate in the fractional divider register
(Table 14–284).
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR (Table 14–277) to
enable FIFO.
5. Pins: Select UART pins through the PINSEL registers and pin modes through the
PINMODE registers (Section 8–5).
Remark: UART receive pins should not have pull-down resistors enabled.
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR
(Table 14–278). This enables access to U0/2/3IER (Table 14–274). Interrupts are
enabled in the NVIC using the appropriate Interrupt Set Enable register.
7. DMA: UART0/2/3 transmit and receive functions can operate with the GPDMA
controller (see Table 31–544).

This was very helpful to set up a new component.
But i have not found a similar description in the user manuals of LPC1114 nor LPC1343.
Is there something similar in a different document (which i have not seens yet),
perhaps some kind of application note ?

Thanks for helping me with some basic clarifications !

Regards,

Martin

Re: Differences LPC1114 (Cortex-M0) / LPC1343 (Cortex-M3) / LPC1768 (Cortex-M3)...

lpcware — Thu, 16 Jun 2016 00:51:05 GMT

Content originally posted in LPCWare by rkiryanov on Sat Jan 30 14:18:13 MST 2010

Quote: capiman
But then the LPC1114 is a Cortex-M0.
Is Cortex-M0 and Cortex-M3 binary compatible and only execution / internal handling is different?

Cortex-M3: Thumb-2, MPU
Cortex-M0: Thumb-2 subset (16-bit Thumb instructions & BL, MRS, MSR, ISB, DSB, and DMB)

See "ARMv7-M Architecture Reference Manual" and "ARMv6-M Architecture Reference Manual" on arm.com.

LPCXpresso IDE中的主题 Differences LPC1114 (Cortex-M0) / LPC1343 (Cortex-M3) / LPC1768 (Cortex-M3)...

Differences LPC1114 (Cortex-M0) / LPC1343 (Cortex-M3) / LPC1768 (Cortex-M3)...

Re: Differences LPC1114 (Cortex-M0) / LPC1343 (Cortex-M3) / LPC1768 (Cortex-M3)...