topic Re: Interrupts are themselves interruptable? in LPCXpresso IDE https://community.nxp.com/t5/LPCXpresso-IDE/Interrupts-are-themselves-interruptable/m-p/556703#M14248 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by gbm on Tue Mar 06 01:20:23 MST 2012</STRONG><BR /><SPAN>Cortex M has preemptive multilevel interrupts. An interupt will interrupt another if it's priority is logically higher (numerically lower) than the currently-servicd one. Initially all priorities are set as highest - 0.</SPAN><BR /><BR /><SPAN>All of this is descibed in ARM manuals and in a section on Cortex M core in NXP manual.</SPAN></BODY></HTML> Thu, 16 Jun 2016 02:07:02 GMT lpcware 2016-06-16T02:07:02Z Interrupts are themselves interruptable? https://community.nxp.com/t5/LPCXpresso-IDE/Interrupts-are-themselves-interruptable/m-p/556702#M14247 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by menhwa on Tue Mar 06 00:48:15 MST 2012</STRONG><BR /><SPAN>With LPC1113/302, I has enabled two interrupts source: I2C interrupt and 32-bit timer0 interrupt.</SPAN><BR /><BR /><SPAN>If I set I2C interrupt as priority 0, and 32-bit Timer0 interrupt as priority 1. During serving of 32-bit Timer0 interrupt, if I2C interrupt is triggered, will the timer0 interrupt been halted and serve the I2C interrupt? Or I2C interrupt only been served after the 32-bit interrupt?</SPAN><BR /><BR /><SPAN>Sorry as I confuse with the concept. Thanks.</SPAN></BODY></HTML> Thu, 16 Jun 2016 02:07:02 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Interrupts-are-themselves-interruptable/m-p/556702#M14247 lpcware 2016-06-16T02:07:02Z Re: Interrupts are themselves interruptable? https://community.nxp.com/t5/LPCXpresso-IDE/Interrupts-are-themselves-interruptable/m-p/556703#M14248 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by gbm on Tue Mar 06 01:20:23 MST 2012</STRONG><BR /><SPAN>Cortex M has preemptive multilevel interrupts. An interupt will interrupt another if it's priority is logically higher (numerically lower) than the currently-servicd one. Initially all priorities are set as highest - 0.</SPAN><BR /><BR /><SPAN>All of this is descibed in ARM manuals and in a section on Cortex M core in NXP manual.</SPAN></BODY></HTML> Thu, 16 Jun 2016 02:07:02 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Interrupts-are-themselves-interruptable/m-p/556703#M14248 lpcware 2016-06-16T02:07:02Z