LPCXpresso IDEのトピックRe: SPI - full duplex communication

SPI - full duplex communication

lpcware — Wed, 15 Jun 2016 23:30:26 GMT

Content originally posted in LPCWare by tyassin on Thu Aug 15 06:19:03 MST 2013
Hello,

I have a quetion on how the SPI work when there is communication between two LPC's.
I have a setup where two MCUs are connected together(LPC1114) whith MOSI-MOSI, MISO-MISO, CLK-CLK and SSEL-SSEL connected together. If I do not want to use interrupts how or when does the slave pick up the data?
Do you make a while loop where it waits until SSEL is toggled low or how????

Another question is regarding the flow of the data. IS it correct when the master toggle SSEL that both the master and the slave can write to its respectively DR-register or is there a certain sequence this has to happen?

I have read the datasheet several times but am really not sure about these things. So will appriciate it a lot if someone could explain.

Thank you.

Regards.

Re: SPI - full duplex communication

lpcware — Wed, 15 Jun 2016 23:30:27 GMT

Content originally posted in LPCWare by ECamino on Thu Aug 15 07:52:07 MST 2013
Hi,

If there is data ready for tx on MISO, then the clock signal makes the slave send it out to the master making the com full duplex.

In your main loop, why not create a function that will read the appropriate registers (not sure, but my guess would be TX/RTRIS or TX/RTMIS?) to see if there is data tx/rx ready? If so, you can set a flag or change a state, return and continue. This way you poll the SPI (no interrupts) and be non-blocking.

Have you searched for example code from LPCware or LPCXpresso?

EC

Re: SPI - full duplex communication

lpcware — Wed, 15 Jun 2016 23:30:27 GMT

Content originally posted in LPCWare by tyassin on Thu Aug 15 12:09:30 MST 2013
Hi

Ok I see. So in principle the slave can write a single byte to its data register and then do something else and when the master then starts to communicate, this data will be send to the master?
You are right there are a status register which indicate if the FIFO is full or not full or whether the SPI is idle or sending/receiving a frame. I guess it is this register you refer to.

There are examples which I have looked at, but I am not completely sure how they operate.

Thank you for your reply