topic Re: Wait state adjustments in LPCXpresso IDE https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528873#M1183 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by domen on Mon Nov 08 02:24:21 MST 2010</STRONG><BR /><SPAN>It's not that simple.</SPAN><BR /><BR /><SPAN>Flash transfers go through ICode bus... wait states are for that bus, they don't necessary stall the CPU. Also, yes, 32-bit fetches mean 2 thumb instructions can be fetched at once. And then there's 64-bit cache.</SPAN><BR /><BR /><SPAN>To sum it up: Flash interface on cortex-m3 is quite smart. IIRC you don't even get speed increases when running code from RAM.</SPAN><BR /><BR /><SPAN>Or you could just benchmark it, to see it really makes a difference.</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:03:28 GMT lpcware 2016-06-15T23:03:28Z Wait state adjustments https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528869#M1179 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by Brinkand on Wed Sep 22 01:31:54 MST 2010</STRONG><BR /><SPAN>I am using an LPC1311, which I am clocking down to 48MHz. I recall that there should be 3 wait states et 72MHz, but I cannot find the information anywhere.</SPAN><BR /><BR /><SPAN>Please help me find:</SPAN><BR /><BR /><SPAN>Information on wait states?</SPAN><BR /><BR /><SPAN>How do I reduce the wait states?</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:03:25 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528869#M1179 lpcware 2016-06-15T23:03:25Z Re: Wait state adjustments https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528870#M1180 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by domen on Wed Sep 22 02:34:14 MST 2010</STRONG><BR /><SPAN>User's manual, Flash memory access, FLASHCFG register.</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:03:26 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528870#M1180 lpcware 2016-06-15T23:03:26Z Re: Wait state adjustments https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528871#M1181 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by Brinkand on Wed Sep 22 05:03:21 MST 2010</STRONG><BR /><SPAN>Thank You very much.</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:03:26 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528871#M1181 lpcware 2016-06-15T23:03:26Z Re: Wait state adjustments https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528872#M1182 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by cyberstudio on Sat Nov 06 15:19:49 MST 2010</STRONG><BR /><SPAN>It appears that by default, it is 3 wait states. How wide is the flash memory bus? (The average instruction is 16-bits wide so for example will it read 2 instructions at a time?)</SPAN><BR /><BR /><SPAN>If not, then what is the point of setting the system clock frequency higher? 1 wait state at 20MHz and 2 wait states at 40MHz is going to be the same speed (e.g. as in LPC11xx) and 3 wait states at 50MHz will end up actually being slower.</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:03:27 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528872#M1182 lpcware 2016-06-15T23:03:27Z Re: Wait state adjustments https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528873#M1183 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by domen on Mon Nov 08 02:24:21 MST 2010</STRONG><BR /><SPAN>It's not that simple.</SPAN><BR /><BR /><SPAN>Flash transfers go through ICode bus... wait states are for that bus, they don't necessary stall the CPU. Also, yes, 32-bit fetches mean 2 thumb instructions can be fetched at once. And then there's 64-bit cache.</SPAN><BR /><BR /><SPAN>To sum it up: Flash interface on cortex-m3 is quite smart. IIRC you don't even get speed increases when running code from RAM.</SPAN><BR /><BR /><SPAN>Or you could just benchmark it, to see it really makes a difference.</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:03:28 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528873#M1183 lpcware 2016-06-15T23:03:28Z Re: Wait state adjustments https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528874#M1184 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by ataru on Wed Dec 01 08:42:36 MST 2010</STRONG><BR /><SPAN>Any reason the flashcfg register is not included in this header file, at least as far as I can tell ?</SPAN></BODY></HTML> Wed, 15 Jun 2016 23:03:28 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Wait-state-adjustments/m-p/528874#M1184 lpcware 2016-06-15T23:03:28Z