https://community.nxp.com/t5/LPCXpresso-IDE/Serial-Wire-Debug-Rising-edge-or-falling-edge/m-p/550124#M11288 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by JUM on Thu Jul 28 06:48:45 MST 2011</STRONG><BR /><SPAN>Hi, </SPAN><BR /><SPAN>according to Figures 5-1 and 5-2 in "ARM® Debug Interface v5 Architecture Specification" the data bits on SWDIO are valid at the falling edge of SWCLK.</SPAN><BR /><SPAN>BUT: According to Figures 24 and 25 in "ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement" the data bits on SWDIO are valid at the rising edge of SWCLK!?</SPAN><BR /><SPAN>What is true?</SPAN><BR /><SPAN>Best regards</SPAN><BR /><SPAN>JUM</SPAN></BODY></HTML> Wed, 15 Jun 2016 22:07:59 GMT lpcware 2016-06-15T22:07:59Z https://community.nxp.com/t5/LPCXpresso-IDE/Serial-Wire-Debug-Rising-edge-or-falling-edge/m-p/550124#M11288 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by JUM on Thu Jul 28 06:48:45 MST 2011</STRONG><BR /><SPAN>Hi, </SPAN><BR /><SPAN>according to Figures 5-1 and 5-2 in "ARM® Debug Interface v5 Architecture Specification" the data bits on SWDIO are valid at the falling edge of SWCLK.</SPAN><BR /><SPAN>BUT: According to Figures 24 and 25 in "ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement" the data bits on SWDIO are valid at the rising edge of SWCLK!?</SPAN><BR /><SPAN>What is true?</SPAN><BR /><SPAN>Best regards</SPAN><BR /><SPAN>JUM</SPAN></BODY></HTML> Wed, 15 Jun 2016 22:07:59 GMT https://community.nxp.com/t5/LPCXpresso-IDE/Serial-Wire-Debug-Rising-edge-or-falling-edge/m-p/550124#M11288 lpcware 2016-06-15T22:07:59Z