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    <title>LPCXpresso IDEのトピックRe: Cortex-M0 Atomic/integral access</title>
    <link>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548329#M10495</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by rocketdawg on Wed May 14 09:26:53 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;variable access may not be atomic and M0 do not have bit band&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;start some where near here&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Finfocenter.arm.com%2Fhelp%2Findex.jsp%3Ftopic%3D%2Fcom.arm.doc.dai0321a%2FBIHBIHDF.html" rel="nofollow" target="_blank"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHBIHDF.html&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 23:25:40 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T23:25:40Z</dc:date>
    <item>
      <title>Cortex-M0 Atomic/integral access</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548326#M10492</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by JoWi on Wed May 14 01:02:13 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am currently mirgrating from 8051 to M0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;For simple IRQ&amp;lt;-&amp;gt;UserSoftware comunication the 8051 had 1-bit flags. What is the smallest way (without disabling IRQs) to replace this on the M0 or do I have to use 32-bit ints?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks, Jo&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:25:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548326#M10492</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:25:37Z</dc:date>
    </item>
    <item>
      <title>Re: Cortex-M0 Atomic/integral access</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548327#M10493</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by wmues on Wed May 14 05:45:58 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;You might use any 8bit, 16bit or 32bit memory location to replace "flag bits".&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Do not use C bitfields!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Don't forget to add the "volatile" keyword if you want interrupt communication!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;volatile unsigned char/short/int this_is_a_flag;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:25:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548327#M10493</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:25:38Z</dc:date>
    </item>
    <item>
      <title>Re: Cortex-M0 Atomic/integral access</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548328#M10494</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by JoWi on Wed May 14 06:44:57 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Ok, Thx ;-)&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:25:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548328#M10494</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:25:39Z</dc:date>
    </item>
    <item>
      <title>Re: Cortex-M0 Atomic/integral access</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548329#M10495</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by rocketdawg on Wed May 14 09:26:53 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;variable access may not be atomic and M0 do not have bit band&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;start some where near here&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Finfocenter.arm.com%2Fhelp%2Findex.jsp%3Ftopic%3D%2Fcom.arm.doc.dai0321a%2FBIHBIHDF.html" rel="nofollow" target="_blank"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHBIHDF.html&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:25:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/Cortex-M0-Atomic-integral-access/m-p/548329#M10495</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:25:40Z</dc:date>
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