Clock configuration

lpcware — Wed, 15 Jun 2016 18:17:21 GMT

Content originally posted in LPCWare by LSchuch on Fri Feb 06 10:37:03 MST 2015
Hello!

I am trying to configure the base clock following the User Manul instructions (see below). In order to verify if I am doing correct, I am also enabling the BASE_OUT_CLK pin and selecting the PLL1 as clock source.

But I am not getting any good signal in the BASE_OUT_CLK pin. Probably I am missing something in the configurations.

1. Select the IRC an BASE_M3_CLK source.
2. Enable the crystal oscillator (see Table 110).
3. Wait 250 s.
4. Reconfigure PLL1 as follows (see Table 121):
– Select the M and N divider values to produce the final desired PLL1 output
frequency foutPLL.
– Select the crystal oscillator as clock source for PLL1.
5. Wait for the PLL1 to lock.
6. Set the PLL1 P-divider to divide by 2 (DIRECT = 0, PSEL=0).
7. Select PLL1 as BASE_M3_CLK source. The BASE_M3_CLK now operates in the
mid-frequency range.
8. Wait 50 s.
9. Set the PLL1 P-divider to direct output mode (DIRECT = 1).

You can find my code below:

   // Configures clock output pin
   LPC_SCU->SFSP1_19 = 0x04;

   // Reference page 130
   // 1. Select the IRC an BASE_M3_CLK source.
   LPC_CGU->BASE_M3_CLK |= 0x01000000;
   LPC_CGU->BASE_M3_CLK &= (~0x1E000000);

   // 2. Enable the crystal oscillator (see Table 110).
   LPC_CGU->XTAL_OSC_CTRL &= CLEAR_BIT2; // Selects low frequency mode (12MHz)
   LPC_CGU->XTAL_OSC_CTRL &= CLEAR_BIT0; // Enables crystal

   // 3. Wait 250ms.
   for(i=0;i<10000;i++)
   __asm("NOP");

   // 4. Reconfigure PLL1 as follows (see Table 121):
   // – Select the M and N divider values to produce the final desired PLL1 output frequency foutPLL.
   LPC_CGU->PLL1_CTRL |= 0x00322100; // P=2 , N = 3, M = 50 (100Mhz)
   LPC_CGU->PLL1_CTRL &= (~0x00CD1200);

   // – Select the crystal oscillator as clock source for PLL1.
   LPC_CGU->PLL1_CTRL |= 0x06000000; // bits 28:24 - crystal oscillator = 0x06
   LPC_CGU->PLL1_CTRL &= (~0x19000000);

   // 5. Wait for the PLL1 to lock.
   while((LPC_CGU->PLL1_STAT & SET_BIT0) == 1);

   // 6. Set the PLL1 P-divider to divide by 2 (DIRECT = 0, PSEL=0).
   LPC_CGU->PLL1_CTRL &= CLEAR_BIT7; // Direct = 0
   LPC_CGU->PLL1_CTRL &= CLEAR_BIT8; // PSEL = 0

   // 7. Select PLL1 as BASE_M3_CLK source. The BASE_M3_CLK now operates in the mid-frequency range.
   LPC_CGU->BASE_M3_CLK |= 0x09000000; // bits 28:24 - PLL1 = 0x09
   LPC_CGU->BASE_M3_CLK &= (~0x16000000);

   // Select PLL1 as BASE_OUT_CLK source.
   LPC_CGU->BASE_OUT_CLK |= 0x09000000; // bits 28:24 - PLL1 = 0x09
   LPC_CGU->BASE_OUT_CLK &= (~0x16000000);

   // 8. Wait 50ms.
   for(i=0;i<2000;i++)
   __asm("NOP");

   // 9. Set the PLL1 P-divider to direct output mode (DIRECT = 1).
   LPC_CGU->PLL1_CTRL |= SET_BIT7; // Direct = 1

Re: Clock configuration

lpcware — Wed, 15 Jun 2016 18:17:22 GMT

Content originally posted in LPCWare by embd02161991 on Fri Feb 06 16:34:06 MST 2015
Hi,

Have you looked at the LPCOpen examples ? Its a good starting point to look at the clock configuration flow.

http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc18xx-packages-0

LPC MicrocontrollersのトピックClock configuration

Clock configuration

Re: Clock configuration