<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic SPIFI with multiple flash memories in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/SPIFI-with-multiple-flash-memories/m-p/526963#M9304</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by busby on Tue May 06 10:03:10 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have a quad SPI serial flash memory connected to the LPC1837 SPIFI peripheral.&amp;nbsp; Using the ROM driver/api I can successfully erase, write to and read from the device.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I now want to extend the system by adding a second flash memory chip (single SPI type).&amp;nbsp; I shall add hardware to gate the SPIFI chip select line to one or other of the memories, selected using a GPIO port.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In my application I want to be able to interleave reading blocks of data from one memory and writing them to the other.&amp;nbsp; As well as setting the chip select routing, will it be necessary to reset the SPIFI peripheral and/or the serial flash devices when switching between them?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Chris&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:15:03 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:15:03Z</dc:date>
    <item>
      <title>SPIFI with multiple flash memories</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/SPIFI-with-multiple-flash-memories/m-p/526963#M9304</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by busby on Tue May 06 10:03:10 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have a quad SPI serial flash memory connected to the LPC1837 SPIFI peripheral.&amp;nbsp; Using the ROM driver/api I can successfully erase, write to and read from the device.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I now want to extend the system by adding a second flash memory chip (single SPI type).&amp;nbsp; I shall add hardware to gate the SPIFI chip select line to one or other of the memories, selected using a GPIO port.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In my application I want to be able to interleave reading blocks of data from one memory and writing them to the other.&amp;nbsp; As well as setting the chip select routing, will it be necessary to reset the SPIFI peripheral and/or the serial flash devices when switching between them?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Chris&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:15:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/SPIFI-with-multiple-flash-memories/m-p/526963#M9304</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:15:03Z</dc:date>
    </item>
    <item>
      <title>Re: SPIFI with multiple flash memories</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/SPIFI-with-multiple-flash-memories/m-p/526964#M9305</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by bavarian on Wed May 14 08:46:41 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Well, sounds feasable if you use the memory just for write/read purposes. If you do code execution then I expect problems.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Sinply test it, I would use 2 memories of the same type for that.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;NXP Support Team&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:15:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/SPIFI-with-multiple-flash-memories/m-p/526964#M9305</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:15:03Z</dc:date>
    </item>
  </channel>
</rss>

