topic Re: ADC Channel 0, 1 crosstalk? in LPC Microcontrollers

ADC Channel 0, 1 crosstalk?

lpcware — Wed, 15 Jun 2016 17:05:03 GMT

Content originally posted in LPCWare by tomg on Tue Apr 26 06:21:21 MST 2016
I'm narrowed a bug down to a LPCxpresso V2 demo board with connected trimmers to provide analog signal to channel 0 and 1. I'm seeing some "crosstalk"(?) between channels:

Sampling frequncy set to max (Chip_ADC_SetClockRate(LPC_ADC0, ADC_MAX_SAMPLE_RATE);)
Channel 1 set to ~ vref/2 (2029)
This is done, while Channel 0 is at ~ max (4094)
If Channel 0 set to ~ 0, Channel 1 value will become 1675
So I'm seeing an offset of 354 lsb on Channel 1, if Channel 0 changes full range.

if Channel 1 is set to ~ 0, the offset will be 179 and if Channel 1 is set to ~ max, the offset is 206. These offsets are quiet stable/reproduceable.

I checked input values with a scope and they were stable.

If Sampling frequency set to 1/4 * max (Chip_ADC_SetClockRate(LPC_ADC0, ADC_MAX_SAMPLE_RATE / 4);) this doesn't occure anymore (on oversampling there is still about 0.875 lsb impact, but that's tolerable)

Is this some known issue with this chip, or am I unable to understand whats happening here:) ?

greetings
Tom

Re: ADC Channel 0, 1 crosstalk?

lpcware — Sun, 19 Jun 2016 01:09:17 GMT

bump

Re: ADC Channel 0, 1 crosstalk?

mppt — Fri, 14 Dec 2018 13:14:10 GMT

Exactly the same here, cause and solution already found?

Re: ADC Channel 0, 1 crosstalk?

ianbenton — Fri, 28 Dec 2018 14:41:58 GMT

Sounds like an acquisition time problem to me. Does it also go away if you use a lower value of potentiometer?

Re: ADC Channel 0, 1 crosstalk?

mppt — Tue, 15 Jan 2019 10:00:03 GMT

In my case it concerns the LPC15 with custom hardware on which the ADC channels are connected to opamp outputs. Between opamp output and ADC input there is a 10 Ohm, 100 nF LPF so there is 100 nF on the ADC input pins.

All ADC input pin voltages are fixed and show no disturbance during the entire ADC sequence.

Lowering the ADC clock frequency (below 48 MHz) lowers the negative offset.

Only an ADC clock frequency below 4MHz shows acceptable results with still a slight negative offset.