UART0 LSR self-clearing

lpcware — Wed, 15 Jun 2016 17:01:25 GMT

Content originally posted in LPCWare by Scribe on Mon Jan 14 07:24:06 MST 2013
Hi guys,

I'm suffering from a little confusion. I'm banging a few bytes over to an LPC1227 running in 485 mode, they're reaching the FIFO buffer but at no stage is the RBR interrupt being triggered and, when I use Keil's Debug View to inspect UART0, the LSR appears to be clearing itself, even though it's not meant to clear until it has been read.

Other interrupts such as RX Line Interrupt appear to trigger just fine.

Any ideas?

Many thanks

Re: UART0 LSR self-clearing

lpcware — Wed, 15 Jun 2016 17:01:26 GMT

Content originally posted in LPCWare by jgorsk on Mon Mar 11 05:20:41 MST 2013
Hi,

I'm not sure if that's the case with your micro, but Keil debugger
is reading out the receiver fifo when the UART register view window
is on. It reads all the other relevant registers making debugging impossible.

Try testing your program with the uart register view closed. That might help.

LPC MicrocontrollersのトピックUART0 LSR self-clearing

UART0 LSR self-clearing

Re: UART0 LSR self-clearing