LPC MicrocontrollersのトピックRe: Picking up the best pll configuration automatically

Picking up the best pll configuration automatically

lpcware — Wed, 15 Jun 2016 18:11:23 GMT

Content originally posted in LPCWare by farcaller on Fri Jun 13 07:51:43 MST 2014
I'm trying to write an algorithm that would pick the best available PLL0 configuration for the user, given F_in and F_cclk. For now, I don't care about USB clocking.

Let's say the user has mbed board (external 12MHz crystal) that he wants clocked at 100MHz, so the input is:

F_in = 12MHz
F_cclk = 100MHz

The manual says that I should pick higher F_ref if possible for a more stable PLL, for low frequency input clock. What is considered a "low frequency", though?

Also, I can get quite flexible with F_cco value, given that it's later passed through a divisor. So I have two flexibility points here:

[list]
[*] prefer higher M/N pair to lower M/N (i.e. prefer higher F_ref to lower F_ref)
[*] prefer higher F_cco/divisor to lower F_cco/divisor
[/list]

Is there any generic rule which one of those I should prefer? What is better, m=50, n=3, divisor=4, or, say, m=325, n=26, divisor=3?

Re: Picking up the best pll configuration automatically

lpcware — Wed, 15 Jun 2016 18:11:24 GMT

Content originally posted in LPCWare by mc on Fri Jun 13 10:43:58 MST 2014
Hi farcaller,
We have PLL calculator excel sheet which calculates right combinations of M and N. Please check it at
http://www.lpcware.com/content/nxpfile/lpc17xx-pll0-calculator

Re: Picking up the best pll configuration automatically

lpcware — Wed, 15 Jun 2016 18:11:25 GMT

Content originally posted in LPCWare by farcaller on Fri Jun 13 11:54:13 MST 2014
Yes, I know, I'm actually referring to it in my question. To make it even more simple, given that spreadsheet, how do I
a) figure best F_cco (if I don't care about usb)
b) figure best m/n pair from the proposed list

?

Re: Picking up the best pll configuration automatically

lpcware — Wed, 15 Jun 2016 18:11:25 GMT

Content originally posted in LPCWare by farcaller on Tue Jun 17 00:54:50 MST 2014
I got some advice on this on electronics stackexchange: http://electronics.stackexchange.com/questions/115311/optimal-configuration-for-pll-on-lpc17xx

Re: Picking up the best pll configuration automatically

lpcware — Wed, 15 Jun 2016 18:11:26 GMT

Content originally posted in LPCWare by nxp_apps on Fri Jun 20 12:40:45 MST 2014
Hi,

Lowest FCCO output would be ideal if you need lowest power consumption from the PLL.

Thanks.

nxp support

Re: Picking up the best pll configuration automatically

lpcware — Wed, 15 Jun 2016 18:11:27 GMT

Content originally posted in LPCWare by Pacman on Fri Jun 20 14:03:11 MST 2014

Quote: nxp_apps
Lowest FCCO output would be ideal

Yes, absolutely! Lowest FCCO, also because it makes your PLL more stable.
(I found out that a high FCCO might make your PLL more imprecise).

Note: Just so you're aware: Different chip families have different clocking rules.
That means: LPC176x and LPC175x have the same rule, but LPC43xx have different rules.
I do not know if LPC177x and LPC178x can share the LPC176x and LPC175x clock setup code; my guess is that they can't.