<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LPC MicrocontrollersのトピックLPC1778 CAN Block Registers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1778-CAN-Block-Registers/m-p/524383#M7019</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by MikeSimmonds on Sat Oct 25 16:49:34 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The same CAN block may be used in other MCUs but my board is using the LPC1778.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am referring to UM10470 Rev 3 12th March 2014.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The 'bus error' bits (16..23) in the 'Interrupt and Capture' register (for each implemented CAN block)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;appear to be 'stickey'.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Once a bus error has occured, subsequent valid transmissions(s) or reception(s) do not appear to&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;'reset' these bits. They only change (but never zero) if another bus error is observed. [Or a chip reset is given.]&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;From the UM 20.7.4 p572&lt;/SPAN&gt;&lt;BR /&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: &lt;/STRONG&gt;&lt;BR /&gt;The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read &lt;BR /&gt;from CANxICR, regardless of whether part or all of the register is read. This means that &lt;BR /&gt;software should always read CANxICR as a word, and process and deal with all bits of the &lt;BR /&gt;register as appropriate for the application. &lt;/SPAN&gt;&lt;HR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How may I reset (clear) these bits in this read-only register programatically (i.e. via code)?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I have tried reading the register (bits 1..10 are documented as clearing on read) before, during, and after&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;placing the block in and then out of 'reset mode' [via the CAN Mode register] but to no avail.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;On a, possibly, similar note, the 'transmission complete' bit [bit 3] in the CAN Global Status register&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;remains clear (unset) [after a failed transmission] even after an 'Abort' command is given [via the&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;CAN Command register]. It only becomes set again after a successful transmission [or chip reset].&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Again, how can I cause this bit to be set (i.e. error to be cleared) via code.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards, Mike.&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:06:42 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:06:42Z</dc:date>
    <item>
      <title>LPC1778 CAN Block Registers</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1778-CAN-Block-Registers/m-p/524383#M7019</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by MikeSimmonds on Sat Oct 25 16:49:34 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The same CAN block may be used in other MCUs but my board is using the LPC1778.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am referring to UM10470 Rev 3 12th March 2014.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The 'bus error' bits (16..23) in the 'Interrupt and Capture' register (for each implemented CAN block)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;appear to be 'stickey'.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Once a bus error has occured, subsequent valid transmissions(s) or reception(s) do not appear to&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;'reset' these bits. They only change (but never zero) if another bus error is observed. [Or a chip reset is given.]&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;From the UM 20.7.4 p572&lt;/SPAN&gt;&lt;BR /&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: &lt;/STRONG&gt;&lt;BR /&gt;The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read &lt;BR /&gt;from CANxICR, regardless of whether part or all of the register is read. This means that &lt;BR /&gt;software should always read CANxICR as a word, and process and deal with all bits of the &lt;BR /&gt;register as appropriate for the application. &lt;/SPAN&gt;&lt;HR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How may I reset (clear) these bits in this read-only register programatically (i.e. via code)?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I have tried reading the register (bits 1..10 are documented as clearing on read) before, during, and after&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;placing the block in and then out of 'reset mode' [via the CAN Mode register] but to no avail.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;On a, possibly, similar note, the 'transmission complete' bit [bit 3] in the CAN Global Status register&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;remains clear (unset) [after a failed transmission] even after an 'Abort' command is given [via the&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;CAN Command register]. It only becomes set again after a successful transmission [or chip reset].&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Again, how can I cause this bit to be set (i.e. error to be cleared) via code.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards, Mike.&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:06:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1778-CAN-Block-Registers/m-p/524383#M7019</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:06:42Z</dc:date>
    </item>
    <item>
      <title>Re: LPC1778 CAN Block Registers</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1778-CAN-Block-Registers/m-p/524384#M7020</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by MikeSimmonds on Sat Oct 25 18:08:07 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I see that UM10470 rev 3.1 was released on 15th September 2014, but I see no apparent changes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;to the documentation of the CAN 'Global Status' and 'Interrupt and Capture' registers.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Mike.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:06:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1778-CAN-Block-Registers/m-p/524384#M7020</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:06:43Z</dc:date>
    </item>
  </channel>
</rss>

