LPC MicrocontrollersのトピックRe: LPC1788 with SRAM Problem??

LPC1788 with SRAM Problem??

lpcware — Wed, 15 Jun 2016 18:05:34 GMT

Content originally posted in LPCWare by AkshayHV on Thu Jan 22 06:03:39 MST 2015
Hello

I am using a LPC 1788 controller with SRAM W241024A 128K * 8 for storing data. The problem that i am facing is whenever i write data into my SRAM and try to read the data the data i get is the last byte of the previously written data.for example if i write"ABCDEFGH" into the SRAM the I try to read the same data from SRAM I am getting "HHHHHHHH".the initialization function is as below and I am using WE pin as GPIO and controlling it manually while reading and writing.

void SRAMInit( void )
{
volatile uint32_t i;
volatile unsigned long Dummy;
#if 1
//data lines//
LPC_IOCON->P3_0 = 0x21;
LPC_IOCON->P3_1 = 0x21;
LPC_IOCON->P3_2 = 0x21;
LPC_IOCON->P3_3 = 0x21;
LPC_IOCON->P3_4 = 0x21;
LPC_IOCON->P3_5 = 0x21;
LPC_IOCON->P3_6 = 0x21;
LPC_IOCON->P3_7 = 0x21;
#else
//data lines//
LPC_IOCON->P3_16 = 0x21;
LPC_IOCON->P3_17= 0x21;
LPC_IOCON->P3_18 = 0x21;
LPC_IOCON->P3_19= 0x21;
LPC_IOCON->P3_20= 0x21;
LPC_IOCON->P3_21= 0x21;
LPC_IOCON->P3_22= 0x21;
LPC_IOCON->P3_23= 0x21;
#endif
//address lines//
LPC_IOCON->P4_0 = 0x21;
LPC_IOCON->P4_1 = 0x21;
LPC_IOCON->P4_2 = 0x21;
LPC_IOCON->P4_3 = 0x21;
LPC_IOCON->P4_4 = 0x21;
LPC_IOCON->P4_5 = 0x21;
LPC_IOCON->P4_6 = 0x21;
LPC_IOCON->P4_7 = 0x21;
LPC_IOCON->P4_8 = 0x21;
LPC_IOCON->P4_9 = 0x21;
LPC_IOCON->P4_10 = 0x21;
LPC_IOCON->P4_11 = 0x21;
LPC_IOCON->P4_12 = 0x21;
LPC_IOCON->P4_13 = 0x21;
LPC_IOCON->P4_14 = 0x21;
LPC_IOCON->P4_15 = 0x21;
LPC_IOCON->P5_0 = 0x21;

LPC_IOCON->P4_24 = 0x21;
//LPC_IOCON->P4_25 = 0x21;

LPC_IOCON->P4_31 = 0x00;
LPC_GPIO4->DIR |= (1<<31);
LPC_GPIO4->SET |= (1<<31);
LPC_IOCON->P4_30 = 0x21;

LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL |= (8<<0);
LPC_SC->EMCDLYCTL |=(8<<8);

LPC_SC->EMCDLYCTL |= (8<<16);
LPC_EMC->Config = 0x80;
LPC_EMC->StaticExtendedWait = 0x00;
LPC_EMC->StaticConfig0 = 0x80;
LPC_EMC->StaticWaitWen0 = 0x01;
LPC_EMC->StaticWaitOen0 = 0x01;
LPC_EMC->StaticWaitRd0 = 0x01;
LPC_EMC->StaticWaitWr0 = 0x01;
LPC_EMC->Control = 0x01;

}

Thanks in advance for any help

regards
Akshay H V

Re: LPC1788 with SRAM Problem??

lpcware — Wed, 15 Jun 2016 18:05:35 GMT

Content originally posted in LPCWare by MikeSimmonds on Thu Jan 22 06:34:35 MST 2015
WHY! are you trying to control one of the EMC interface lines instead of letting the EMC do its job?

I don't know (and am not going to waste any time) on this. Possibly it is down to timing, perhaps not. Who knows?

I'd strongly suggest getting rid of GPIO WE line. If that means a board mod, then so be it.

Mike

Re: LPC1788 with SRAM Problem??

lpcware — Wed, 15 Jun 2016 18:05:36 GMT

Content originally posted in LPCWare by AkshayHV on Thu Jan 22 22:33:40 MST 2015
Hello mike ,

Thanks for reply.The reason why i am using this pin as a GPIO is because i am using both SRAM as well as SDRAM.both since WE will be shared by both SRAM as well as SDRAM for TFT display interfacing i thaught of using it with a GPIO. My SDRAM uses 16 bit data lines and my SRAM uses 8 bit data lines.I have doubt that can we able to use D0 to D15 for SDRAM and D16 to D23 for SRAM.if so are there any necessary measure to take care of.thanks in advance for any replies.

regards
Akshay H V

Re: LPC1788 with SRAM Problem??

lpcware — Wed, 15 Jun 2016 18:05:36 GMT

Content originally posted in LPCWare by MikeSimmonds on Fri Jan 23 03:38:24 MST 2015
Firstly: DO NOT post the SAME question multiple time or in multiple forums!!!
Otherwise people will think you are an idiot and won't answer (more than once at least).

You clearly need to do some research on memory interfacing.

The Data lines and the address lines are shared between the 4 static ram ranges AND the 4 dynamic ram ranges.

As are some of the control lines (such as WE); Others are either for static rams or for dynamic rams.

Although addr/data/control go to both sets of memory chips in parallel, they ony take effect if the chip select
for the chips is active. That is why the various CS pins have different address ranges assigned.

Also BEWARE blindly connecting the addr lines to dynamic memory. They are not really address lines, but
row, column, bank selectors.

Read the UM10470 EMC chapter very very carefully! Read the SDRAM datasheet carefully.
Download schematics of example boards from Keil, EA websites. See also AN10771. [Applies to 1778/1788 too.]

I include a memory schematic. This uses a 16-bit static ram. Just drop D8-D16 and the higher order Addr lines.
There are sample layouts in the UM for static ram.

Regards, Mike