topic Re: Design guidlines for LPC1768 at 100MHz in LPC Microcontrollers

Design guidlines for LPC1768 at 100MHz

lpcware — Wed, 15 Jun 2016 18:01:03 GMT

Content originally posted in LPCWare by johndpar on Thu Apr 03 05:20:23 MST 2014
This is not the usual question about how to set the PLL and dividers. That bit is quite easy!

We have some issues running the LPC1768 at 100MHz, in particular the CAN peripheral does not always accept writes to its registers.

(12MHz crystal with 400MHz PLL and divide by 4 to get 100MHz)

Having dropped the speed to 80MHz the system is working well.

We suspect that our board layout is a problem.

Do you have any design guidelines for placement of decoupling capacitors, their type and value?

Thanks

John Parker

Re: Design guidlines for LPC1768 at 100MHz

lpcware — Wed, 15 Jun 2016 18:01:04 GMT

Content originally posted in LPCWare by LabRat on Thu Apr 03 05:40:29 MST 2014

Quote: johndpar
Do you have any design guidelines for placement of decoupling capacitors, their type and value?

I like the little brown ones :)

Seriously: if you suspect your board is the problem it could be helpful to show it?

Or look at some other boards?

Or just google "decoupling LPC1768" ? (Sorry, can't add links here, SPAM filter is still PITA...)

Re: Design guidlines for LPC1768 at 100MHz

lpcware — Wed, 15 Jun 2016 18:01:04 GMT

Content originally posted in LPCWare by nxp_apps on Mon Apr 07 11:52:01 MST 2014
Hi,

Few questions:

a) Are you running other peripherals besides CAN? Do other peripherals fail?

b) Does the CAN peripheral fail with pclk = ccllk?

Hope to hear your feedback.

Thanks.

nxp_support

Re: Design guidlines for LPC1768 at 100MHz

lpcware — Wed, 15 Jun 2016 18:01:05 GMT

Content originally posted in LPCWare by johndpar on Mon Apr 28 00:45:04 MST 2014
Sorry for taking a while to respond - beed busy with other aspects of the project.

Well it looks like some form of board contamination / dry joint is to blame as the problem has disappeared!

The problem was observed with the CAN bit rate register and with the interrupt enable register. Other peripherals in use include UART, I2C and SPI.

Dropping the cclk to 80MHz fixed the problem, running at 100MHz and the problem cam back. Now on the same board I can run at anything up to 150MHz cclk (!!!) and it is totally stable. I even removed the decoupling capacitors around the 1768 and it still runs at 150MHz. (Yes I do know that the datasheet says it is specified up to 100MHz but I was trying to see if I had a problem.

So for now it looks like the problem is solved.

Thanks anyway.

Regards

John

Re: Design guidlines for LPC1768 at 100MHz

lpcware — Wed, 15 Jun 2016 18:01:06 GMT

Content originally posted in LPCWare by Pacman on Mon Apr 28 01:50:58 MST 2014
Just a note... Make sure, when you configure the PLL, to use the smallest possible values on the divider/multiplier registers. I've noticed, if I'm just sloppy and write the largest available values, I get an unstable frequency.