topic Re: LCD Driver LPC177x_8x_lcd.c clocking question in LPC Microcontrollers

LCD Driver LPC177x_8x_lcd.c clocking question

lpcware — Wed, 15 Jun 2016 18:00:34 GMT

Content originally posted in LPCWare by EReyes on Mon Feb 06 21:44:11 MST 2012
I pulled the latest version on the driver library git repository. When I tried to use the LCD driver I found the clock was not being generated correctly (checked with an oscilloscope).

This is the relevant code (starts at line 114)

<code>
// Set clock
LPC_LCD->POL &= ~(0x01 << 5);
if( pConfig->panel_clk > 0) {
clkdiv = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) / pConfig->panel_clk - 1;
LPC_SC->LCD_CFG = clkdiv & 0x1F;
}
</code>

Shouldn't the fourth line be like this?

clkdiv = CLKPWR_GetCLK( <FONT COLOR="Red">CLKPWR_CLKTYPE_PER</FONT>) / pConfig->panel_clk - 1;

I was under the impression the LCD module is clocked by the peripheral clock and not the core clock.

Re: LCD Driver LPC177x_8x_lcd.c clocking question

lpcware — Wed, 15 Jun 2016 18:00:35 GMT

Content originally posted in LPCWare by Karl on Tue Feb 07 09:17:13 MST 2012
The description of the CLKSEL bit in table 226 says <i>...the clock source for the LCD block is CCLK</i>.

Re: LCD Driver LPC177x_8x_lcd.c clocking question

lpcware — Wed, 15 Jun 2016 18:00:36 GMT

Content originally posted in LPCWare by EReyes on Wed Feb 08 19:14:39 MST 2012
You are right. Turns out I wasn't setting bit 26 on LPC_LCD->POL to bypass the LCD Module's internal clock divider.

Thanks.