LPC MicrocontrollersのトピックRe: LPC5536 and Hyperram

LPC5536 and Hyperram

img_gabrigob — Mon, 24 Nov 2025 18:15:43 GMT

Hello,

I am struggling with the configuration of the FLEXSPI peripheral on a LPC5536JBD100; the hyperram chip is a S27KS0642GABHV020. The system is on a custom board on which we already successfully integrated other features.

I got inspired by AN12239 which is for a different processor but takes as example a very similar chip to the one I am using: it seems to me that the main difference is in the newer node technology for S27KS0642 which makes it faster than the S27KS0641 used in the application node but the timing diagrams (and so the dummy cycles) and the commands are the same.

Another source of inspiration is from this article

https://community.nxp.com/t5/MCX-Microcontrollers-Knowledge/MCX-N947-FlexSPI-Connecting-to-HyperRAM-Analysis-and/ta-p/1988799

which is not for the same processor I am using but explains the meaning of some fields in the configuration data structures.

I also looked at the example lpcxpresso55s36_flexspi_octal_polling_transfer for comparing the FlexSPI configuration (knowing that something must be changed because it targets a flash device).

My symptom is that when I try to read the vendor id, the function does not return kStatus_Success (it returns the value 7001).

I checked that the clock is connected:

CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 0U, true); /*!< Reset FLEXSPICLKDIV divider counter and halt it */

 CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 2U, false); /*!< Set FLEXSPICLKDIV divider to value 2 */

 CLOCK_AttachClk(kPLL0_to_FLEXSPI); /*!< Switch FLEXSPI to PLL0 */

and the pins have been configured with the GUI

The configuration of the perihperal is done as

int config_hr(void)
{
flexspi_config_t config;
uint32_t tempCustomLUT[ARRAY_SIZE(customLUT)] = {0U};
/* Copy LUT information from flash region into RAM region, because flash will be reset and back to single mode;
 In lately time, LUT table assignment maybe failed after flash reset due to LUT read entry is application's
 required mode(such as octal DDR mode) and flash is being in single SDR mode, they don't matched. */
 memcpy(tempCustomLUT, customLUT, sizeof(tempCustomLUT));

/* Get FLEXSPI default settings and configure the flexspi. */
 FLEXSPI_GetDefaultConfig(&config);
/* Init FLEXSPI. */
 config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;//kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;//kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
//config.enableSckBDiffOpt = true;
//config.enableCombination = true;
 config.ahbConfig.enableAHBPrefetch = true;
 config.ahbConfig.enableAHBBufferable = true;
 config.ahbConfig.enableAHBCachable = true;
//
 config.enableDoze = false;

 FLEXSPI_Init(EXAMPLE_FLEXSPI, &config);

/* Configure RAM settings according to serial RAM feature. */
 FLEXSPI_SetFlashConfig(EXAMPLE_FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);

/* Update LUT table. */
 FLEXSPI_UpdateLUT(EXAMPLE_FLEXSPI, 0, tempCustomLUT, ARRAY_SIZE(customLUT));

/* Do software reset. */
 FLEXSPI_SoftwareReset(EXAMPLE_FLEXSPI);
return 0;

}

I checked that we are using the port A1 even in the function that reads the vendor ID

status_t flexspi_hyper_ram_get_id(FLEXSPI_Type *base, uint32_t *vendorId)
{
flexspi_transfer_t flashXfer;
status_t status;
uint32_t id;

/* Write data */
 flashXfer.deviceAddress = 0x0U;
 flashXfer.port = kFLEXSPI_PortA1;
 flashXfer.cmdType = kFLEXSPI_Read;
 flashXfer.SeqNumber = 1;
 flashXfer.seqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_READREG;
 flashXfer.data = &id;
 flashXfer.dataSize = 4;
 status = FLEXSPI_TransferBlocking(base, &flashXfer);
 *vendorId = id & 0xffffU;
return status;
}

The flexspi_device_config_t structure is initialized as follows

flexspi_device_config_t deviceconfig =
{
.flexspiRootClk = 75000000, /* 75MHZ SPI serial clock */
.isSck2Enabled = false,
.flashSize = FLASH_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,
.CSHoldTime = 1,
.CSSetupTime = 1,
.dataValidTime = 1,
.columnspace = 3,
.enableWordAddress = true,
.AWRSeqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA,
.AWRSeqNumber = 1,
.ARDSeqIndex =HYPERRAM_CMD_LUT_SEQ_IDX_READDATA,
.ARDSeqNumber = 0,
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
.AHBWriteWaitInterval = 0,
.enableWriteMask = true,
};

and the LUTs values are

#define LATENCY (0x04)

uint32_t customLUT[20] =
{
/* Read Data */
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READDATA] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READDATA + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READDATA + 2] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

/* Write Data */
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA + 2] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

/* Read Register */
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xE0,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 2] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

/* Write Register */
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY),
[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 2] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
};

which make sense to me because I am using a total of 48 address bits, DDR mode on 8 pads, the commands are correct.

Is there something I am missing?

Re: LPC5536 and Hyperram

Harry_Zhang — Tue, 25 Nov 2025 07:50:51 GMT

Hi @img_gabrigob

About the pin config.

Did you just configure 5 data pins ?

S27KS0642GABHV020 requires an 8 data pins.

Harry

Re: LPC5536 and Hyperram

img_gabrigob — Tue, 25 Nov 2025 10:15:06 GMT

Hello,

thanks.

No, I configured more pins but the screenshot was taken very bad: I suppose there are 8 pin of data one RWDS, one CS_n and a pair of differential clock

Re: LPC5536 and Hyperram

img_gabrigob — Tue, 25 Nov 2025 14:43:36 GMT

hello,

thank you. I replied to you but I think I did something wrong (first time using this community) and the reply went directly to my original post.

Re: LPC5536 and Hyperram

Harry_Zhang — Wed, 26 Nov 2025 09:09:46 GMT

Hi @img_gabrigob

First i think you can check hardware.

Probe the physical signals (scope):

Confirm CK toggles at the rate you expect, CS# pulses for the transaction, and DQ[7:0] / RWDS show activity when you trigger the read-ID sequence.

And reduce FlexSPI serial clock to a low safe frequency (e.g. 20–25 MHz) while you debug.

Then i think you can refer to this LUT.

	/* Read Register */
	[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG] =
		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xE0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
	[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 1] = FLEXSPI_LUT_SEQ(
		kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
	[4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 2] =
		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

	/* Write Register */
	[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG] =
		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
	[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 1] = FLEXSPI_LUT_SEQ(
		kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
	[4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 2] = FLEXSPI_LUT_SEQ(
		kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

RT1064 HyperRAM support S27KS0641 and S27KS0642 - NXP Community

Harry

Re: LPC5536 and Hyperram

img_gabrigob — Fri, 28 Nov 2025 13:53:04 GMT

Hello @Harry_Zhang,

thanks !

I tried to see if there were any differences between my LUT and the one used by the user in the other post you linked but even after trying to adjust the number of dummy in the latency wait state I am still having the same issue.

I don't know if I have misconfigured something on my IDE installation but it seems that on LPC5536 I can not set differential clock from the flexspi_config_t data structure (field enableSckBDiffOpt is inside a disabled ifdef).

We took some measures on the board. The CSN and CLK signal are active.

We captured the clock with two options of slew rate (standard and high)

The clock frequency is slower than I expected it to be (I think that I have set it to 75MHz and here I have 75/2 instead of 150/2).

The data and RWDS signals are stable at 0V. We just see a little glitch (5ns) on the data signals

I am also attaching the pin_mux and clock_config files that are output from the graphical user interface.

Do you have any other suggestions please?

best regards

Re: LPC5536 and Hyperram

Harry_Zhang — Mon, 01 Dec 2025 07:42:03 GMT

Hi @img_gabrigob

Can you share the schematic connection to HyperRAM？

Harry

Re: LPC5536 and Hyperram

img_gabrigob — Mon, 01 Dec 2025 10:39:03 GMT

Hello!

Thanks for the reply

I have checked again the schematic and... I realised that RESN is not controlled by the FLEXspi so I changed the software and made it rise.

Now the controller works, we also configured the pins on the MCU to be with Fast Slew Rate option.

This is the RWDS versus CLK , for example.

So the problems were the values for latency in LUTs (corrected with your link) and the reset.

There's still something I am not understanding even if this is not fundamental for this project but may be useful for future applications: from the configuration in the clock tree I would expect CLK to be at 75MHz but I measured 37.5

Is there any other clock divider I missed?

Thanks,

best regards,

Gabriele

Re: LPC5536 and Hyperram

Harry_Zhang — Tue, 02 Dec 2025 10:07:26 GMT

Hi @img_gabrigob

According to the LPC55S36 data sheet.

The maximum frequency of the clock is 50M(DDR MODE).

/* Flexspi frequency 150MHz / 3 = 50MHz */ CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 0U, true); /*!< Reset FLEXSPICLKDIV divider counter and halt it */ CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 3U, false); /*!< Set FLEXSPICLKDIV divider to value 3 */ CLOCK_AttachClk(kPLL0_to_FLEXSPI); /*!< Switch FLEXSPI to PLL0 */

Harry