LPC546XX CTIMER configuration question

abdel12312 — Thu, 18 Sep 2025 16:05:59 GMT

Hello NXP Community,

I'm working with an LPC546xx and need to know if a single CTIMER can simultaneously:

Use channels 0 and 1 for input capture
Use a match register (MR0) for interrupt generation on counter overflow without affecting any pins

My current setup:

CTIMER1 channels 0-1: Input capture
CTIMER1 channels 2-3: Timeout interrupts

I need to add timer overflow detection using a match register on the same timer. My though was to use Channels 0 or 1 MRs to be able to count number of overflows.

Since MCR (match control), CCR (capture control), and EMR (pin output) are separate registers, I believe they can be configured independently.

Can someone from NXP confirm if using match interrupts alongside input capture is supported?

Re: LPC546XX CTIMER configuration question

Habib_MS — Fri, 26 Sep 2025 23:40:28 GMT

Hello @abdel12312, sorry for the late reply.
Yes, you can configure a channel in Input Capture/Match mode and utilize the match register simultaneously. However, the SDK does not provide an example demonstrating both functionalities together. As a reference, you can modify the example named lpcxpresso54628_ctimer_match_interrupt_example, which already includes the match functionality. This thread may also help guide your implementation.

BR
Habib.

topic Re: LPC546XX CTIMER configuration question in LPC Microcontrollers

LPC546XX CTIMER configuration question

Re: LPC546XX CTIMER configuration question