LPC55S69 USB1 HS PHY PLL initialization

pettel — Fri, 19 Sep 2025 18:15:25 GMT

The documentation (UM11126, Rev. 2.8, Table 850) says for Bit 21 PLL_REG_ENABLE:

SW must set this bit 15 us before settiing PLL_POWER to avoid glitches on PLL output clock.

When I look in the source code of the the SDK (Version 25.6.0) into fsl_clock.c:
2045 │ /* Enable USB PHY clock */
2046 │ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
....

2120 │ USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv;
2121 │ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK;
2122 │ USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0
2123 │ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK;
2124 │ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK;
2125 │
2126 │ USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;

PLL_REG_ENABLE is set in line 2121 and PLL_POWER is set in line 2123 with no regard for the 15 us time delay required in the user manual. Is this function in fsl_clock.c flawed or am I missing something?

Re: LPC55S69 USB1 HS PHY PLL initialization

ZhangJennie — Mon, 22 Sep 2025 04:12:36 GMT

Hi @pettel

I have reviewed both the UM11126 and the SDK implementation for enabling the USB PHY PLL.
According to the UM, software must set the PLL_REG_ENABLE bit at least 15 microseconds before setting PLL_POWER to avoid glitches on the PLL output clock:

However, in the current SDK implementation (fsl_clock.c), PLL_REG_ENABLE and PLL_POWER are set consecutively without any delay in between.

To ensure reliable operation, I suggest adding a 15-microsecond delay between setting PLL_REG_ENABLE and PLL_POWER.

I will report it to the SDK team meanwhile. Thank you so much for bringing the problem to our attention.

Best Regards

Jun Zhang

LPC MicrocontrollersのトピックLPC55S69 USB1 HS PHY PLL initialization

LPC55S69 USB1 HS PHY PLL initialization

Re: LPC55S69 USB1 HS PHY PLL initialization