topic LPC5536 MCAN RF0F Interrupt in LPC Microcontrollers

LPC5536 MCAN RF0F Interrupt

microcris — Wed, 02 Jul 2025 17:15:10 GMT

Hello,

Why am I getting this interrupt (IR:RF0F) if the IE:RF0FE is set to 0?

I'm trying to figure this out by monitoring the IE register and it is changing from 0x3800000 to 0x3800001, the bit number 3 is not being set at anytime.

Best regards,

Cristiano Rodrigues

Re: LPC5536 MCAN RF0F Interrupt

Alice_Yang — Mon, 07 Jul 2025 02:43:16 GMT

Hello @microcris

Thanks for your question.

The flag (IR:RF0F) is automatically set by the hardware and has no relation to the interrupt enable register IE:RF0FE. The IE register notifies the CPU to execute the interrupt handler. Regarding the change of IE bit 0 from 0 to 1, please debug the code to check where this bit is being modified.

Thank you.

Alice

Re: LPC5536 MCAN RF0F Interrupt

microcris — Thu, 24 Jul 2025 20:28:38 GMT

Hello @Alice_Yang!

Thank you for your answer.
It is all fine with the IE register. I was just stating that the IE:RF0FE (it is the bit number 2 and not the bit number 3) was not being set and the and the IR:RF0F was being triggered. If it is an hardware thing, it is all right then.
It is just a little bit annoying to have a kStatus_MCAN_TxIdle and a kStatus_MCAN_UnHandled with result set to kMCAN_RxFifo0FullFlag for every received message.

Re: LPC5536 MCAN RF0F Interrupt

Alice_Yang — Mon, 28 Jul 2025 03:17:14 GMT

Hello @microcris

The flag of kMCAN_RxFifo0FullFlag is to avoid Rx FIFO overflow.

Thank you.

Alice