topic Re: CAN PSR register - RX Flag Stuck After FIFO Count Is Update in LPC Microcontrollers

CAN PSR register - RX Flag Stuck After FIFO Count Is Update

chellapandi_1603 — Tue, 27 May 2025 06:15:19 GMT

Hello everyone,

I'm working on a CAN implementation with external time stamping in microseconds and using a 16-bit timer for the timestamp source. Here's the setup and issue I'm encountering:

System Setup:

CAN controller with external timestamp source (16-bit, in µs).
On every received CAN frame, I read the external timestamp and combine it with the system time to get a full timestamp.
I handle timer overflow using a timer wrap callback, where I log the system time when the 16-bit timer wraps.
FIFO mode is enabled, and I track frames using RXF0S . F0GI and F0FL.

Observations

I check PSR.RX , FIFO count and index in timer wrap call back , FIFO count Is updated but PSR . RX Flag Is Not Clear.
There is no FIFO overrun (RF0L flag is not set).
System is not losing frames, and FIFO seems to update correctly.
However, PSR.RX doesn't clear even though no actual frame is being received at that moment.

My Questions:

Under what exact conditions and time does PSR.RX clears?
Is it safe to rely on PSR.RX to determine whether a frame is being received?

Additional Info:

The goal is to synchronise CAN frame timestamps to a system clock using the external µs timer and timer wrap handling.
I read:
- FIFO count (F0FL)
- FIFO index (F0GI)
- PSR register
Will use those registers to determine the timing of old and current frames.

Re: CAN PSR register - RX Flag Stuck After FIFO Count Is Update

Harry_Zhang — Wed, 28 May 2025 02:56:39 GMT

Hi @chellapandi_1603

May I ask which chip you are using?

Harry

Re: CAN PSR register - RX Flag Stuck After FIFO Count Is Update

chellapandi_1603 — Wed, 28 May 2025 03:55:15 GMT

Hi @harry,

Thanks for the response!

I'm using the LPC55S16 microcontroller, and the CAN interface is configured with the MCAN peripheral from the NXP SDK V2.15.000.

I’ve enabled external timestamping in microseconds (16-bit timer), and I'm syncing it with system time on frame receive and timer overflow. The issue I'm seeing is with the PSR.RX flag staying high even after FIFO count is increased.

Let me know if you need more details about my CAN setup or how I’m handling interrupts and timestamps.

Best regards,
chellapandi N

Re: CAN PSR register - RX Flag Stuck After FIFO Count Is Update

Harry_Zhang — Thu, 29 May 2025 06:30:12 GMT

Hi @chellapandi_1603

Sorry, i checked the Protocol status register(RSR) in LPC55s1x RM.

But i didn't find the RX bit.

Harry

Re: CAN PSR register - RX Flag Stuck After FIFO Count Is Update

chellapandi_1603 — Fri, 30 May 2025 05:00:03 GMT

Hi @harry,

You're absolutely right — I double-checked the PSR register and realized I misinterpreted the status earlier.

The flag I was referring to is actually the ACT[4:3] bits (Activity field).
In my case, it was showing value 0x2, which indicates "receiver active".

Best regards,
Chellapandi N

Re: CAN PSR register - RX Flag Stuck After FIFO Count Is Update

chellapandi_1603 — Mon, 09 Jun 2025 09:45:11 GMT

Just checking if anyone has insights on the ACT bits in PSR and how reliable they are for detecting CAN reception status, especially in relation to FIFO and timestamping logic. Any help would be appreciated!