LPC MicrocontrollersのトピックRe: LPC55S69: CPU lockup while accessing to SYSCON

LPC55S69: CPU lockup while accessing to SYSCON

raz3l — Wed, 26 Mar 2025 14:51:11 GMT

Hi everyone,

I'm running Zephyr (compiled as Non-Secure) on an LPC55S69, flashed at address 0x0. To boot it, I:

Flashed the NS image at 0x0
Manually set the PC via GDB

The system only works if I comment out this clock initialization line:

CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);

Otherwise, it triggers a processor LOCKUP without any visible exception details. I have checked that SAU and MPU are disabled and I have reviewed the Secure AHB Controller (no obvious blocking configurations).

Could a platform-level firewall (e.g., peripheral access control) block this clock register?
Are there other hardware protections I might have missed?

Thanks!

Re: LPC55S69: CPU lockup while accessing to SYSCON

Harry_Zhang — Wed, 02 Apr 2025 08:49:29 GMT

Hi @raz3l

Yes, the LPC55S69 has platform-level security mechanisms that could be restricting access to the clock registers when running in Non-Secure mode.

Harry

Re: LPC55S69: CPU lockup while accessing to SYSCON

raz3l — Thu, 03 Apr 2025 10:15:10 GMT

Hi @Harry_Zhang ,

Could you point me to which platform-level security mechanisms are you referring to?

Re: LPC55S69: CPU lockup while accessing to SYSCON

Harry_Zhang — Thu, 10 Apr 2025 08:21:50 GMT

Hi @raz3l

On the LPC55S69, the platform-level security mechanisms that control peripheral access between Secure and Non-Secure worlds (enabled by ARM TrustZone-M)

Secure AHB Controller (SECURE_AHB / AHB_SECURE_CTRL)

Security access rules for AHB peripherals
Security access rules for AHB peripherals on AHB Slave Port P8. Each peripheral can
have independent security attribute.

Registers: SEC_CTRL_AHB_PORTx_SLAVEy_RULE
These determine whether each peripheral (e.g., SYSCON, CLOCK, IOCON, GPIO) is accessible by:
You can try to test it.

Harry

Re: LPC55S69: CPU lockup while accessing to SYSCON

raz3l — Mon, 12 May 2025 01:51:45 GMT

Thanks!