Re: Cortex-M7 (IMXRT1171) crash

Nexus76 — Fri, 28 Feb 2025 09:12:51 GMT

Thanks Omar,

I have inserted the code generated form MCUXpresso with ConfigTool->Clocks (that we use in our application)

/* * How to setup clock using clock driver functions: * * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. * * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. * * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. * */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Clocks v11.0 processor: MIMXRT1171xxxxx package_id: MIMXRT1171CVM8A mcu_data: ksdk2_0 processor_version: 13.0.2 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" #include "fsl_iomuxc.h" #include "fsl_dcdc.h" #include "fsl_pmu.h" #include "fsl_clock.h" /******************************************************************************* * Definitions ******************************************************************************/ /******************************************************************************* * Variables ******************************************************************************/ /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { BOARD_BootClockRUN(); } #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) /* This function should not run from SDRAM since it will change SEMC configuration. */ AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void)); void UpdateSemcClock(void) { /* Enable self-refresh mode and update semc clock root to 200MHz. */ SEMC->IPCMD = 0xA55A000D; while ((SEMC->INTR & 0x3) == 0) ; SEMC->INTR = 0x3; SEMC->DCCR = 0x0B; /* * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only * need to change the SEMC clock root here. If customer is using their own DCD and * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be * adjusted here to fine tune the SDRAM performance */ CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602; } #endif #endif /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockRUN called_from_default_init: true outputs: - {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz} - {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz} - {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz} - {id: ARM_PLL_CLK.outFreq, value: 1.56 GHz} - {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz} - {id: AXI_CLK_ROOT.outFreq, value: 780 MHz} - {id: BUS_CLK_ROOT.outFreq, value: 240 MHz} - {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz} - {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz} - {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz} - {id: CSSYS_CLK_ROOT.outFreq, value: 132 MHz} - {id: CSTRACE_CLK_ROOT.outFreq, value: 24 MHz} - {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz} - {id: ENET2_CLK_ROOT.outFreq, value: 125 MHz} - {id: ENET_1G_TX_CLK.outFreq, value: 125 MHz} - {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz} - {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz} - {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz} - {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz} - {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz} - {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz} - {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz} - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 198 MHz} - {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz} - {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz} - {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz} - {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz} - {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz} - {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz} - {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz} - {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz} - {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz} - {id: GPT6_CLK_ROOT.outFreq, value: 200/3 MHz} - {id: GPT6_ipg_clk_highfreq.outFreq, value: 200/3 MHz} - {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPSPI1_CLK_ROOT.outFreq, value: 172.8/7 MHz} - {id: LPSPI2_CLK_ROOT.outFreq, value: 172.8/7 MHz} - {id: LPSPI3_CLK_ROOT.outFreq, value: 172.8/7 MHz} - {id: LPSPI4_CLK_ROOT.outFreq, value: 172.8/7 MHz} - {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART1_CLK_ROOT.outFreq, value: 200/3 MHz} - {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz} - {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz} - {id: M7_CLK_ROOT.outFreq, value: 780 MHz} - {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 50 MHz} - {id: OSC_24M.outFreq, value: 24 MHz} - {id: OSC_32K.outFreq, value: 32.768 kHz} - {id: OSC_RC_16M.outFreq, value: 16 MHz} - {id: OSC_RC_400M.outFreq, value: 400 MHz} - {id: OSC_RC_48M.outFreq, value: 48 MHz} - {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz} - {id: SYS_PLL1_CLK.outFreq, value: 1 GHz, locked: true, accuracy: '0.001'} - {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz} - {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} - {id: SYS_PLL2_PFD1_CLK.outFreq, value: 9504/19 MHz} - {id: SYS_PLL2_PFD2_CLK.outFreq, value: 594 MHz} - {id: SYS_PLL2_PFD3_CLK.outFreq, value: 1900.8/7 MHz} - {id: SYS_PLL2_SS_MODULATION.outFreq, value: 1.2 kHz} - {id: SYS_PLL2_SS_RANGE.outFreq, value: 12 MHz} - {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} - {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz} settings: - {id: SOCDomainVoltage, value: OD} - {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} - {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} - {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '1', locked: true} - {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true} - {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '65', locked: true} - {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} - {id: ANADIG_PLL.PLL_VIDEO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} - {id: ANADIG_PLL.SYS_PLL2.denom, value: '20000', locked: true} - {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} - {id: ANADIG_PLL.SYS_PLL2.num, value: '0', locked: true} - {id: ANADIG_PLL.SYS_PLL2_PFD1_DIV.scale, value: '19', locked: true} - {id: ANADIG_PLL.SYS_PLL2_PFD1_MUL.scale, value: '18', locked: true} - {id: ANADIG_PLL.SYS_PLL2_PFD2_DIV.scale, value: '16', locked: true} - {id: ANADIG_PLL.SYS_PLL2_PFD2_MUL.scale, value: '18', locked: true} - {id: ANADIG_PLL.SYS_PLL2_PFD3_DIV.scale, value: '35', locked: true} - {id: ANADIG_PLL.SYS_PLL2_PFD3_MUL.scale, value: '18', locked: true} - {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '20000'} - {id: ANADIG_PLL.SYS_PLL2_SS_MOD_DIV.scale, value: '20000'} - {id: ANADIG_PLL.SYS_PLL2_SS_STEP.scale, value: '1', locked: true} - {id: ANADIG_PLL.SYS_PLL2_SS_STOP.scale, value: '10000', locked: true} - {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '13', locked: true} - {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true} - {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} - {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} - {id: ANADIG_PLL_PLL_VIDEO_CTRL_GATE_CFG, value: Disabled} - {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled} - {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} - {id: ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_CFG, value: Disabled} - {id: ANADIG_PLL_SYS_PLL2_SS_ENABLE_CFG, value: Enabled} - {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} - {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} - {id: ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_CFG, value: Disabled} - {id: ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_CFG, value: Disabled} - {id: ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_CFG, value: Disabled} - {id: ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_CFG, value: Disabled} - {id: CCM.CLOCK_ROOT0.DIV.scale, value: '2', locked: true} - {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} - {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT14.DIV.scale, value: '1', locked: true} - {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT19.DIV.scale, value: '6', locked: true} - {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} - {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true} - {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} - {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT21.DIV.scale, value: '3', locked: true} - {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} - {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true} - {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} - {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT27.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT28.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT29.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3', locked: true} - {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} - {id: CCM.CLOCK_ROOT30.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT31.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT32.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT36.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT37.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT38.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT39.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3', locked: true} - {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK} - {id: CCM.CLOCK_ROOT40.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT41.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT42.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT43.DIV.scale, value: '11', locked: true} - {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK} - {id: CCM.CLOCK_ROOT44.DIV.scale, value: '11', locked: true} - {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK} - {id: CCM.CLOCK_ROOT45.DIV.scale, value: '11', locked: true} - {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK} - {id: CCM.CLOCK_ROOT46.DIV.scale, value: '11', locked: true} - {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK} - {id: CCM.CLOCK_ROOT47.DIV.scale, value: '1', locked: true} - {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT49.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT5.DIV.scale, value: '4', locked: true} - {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} - {id: CCM.CLOCK_ROOT50.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT52.DIV.scale, value: '4', locked: true} - {id: CCM.CLOCK_ROOT52.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} - {id: CCM.CLOCK_ROOT53.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT56.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT57.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT58.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT59.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT6.DIV.scale, value: '1', locked: true} - {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT60.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT61.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT62.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT63.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT64.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT65.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT66.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT67.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT69.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT70.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT71.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT72.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT73.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT74.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT75.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT76.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT77.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT78.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM.CLOCK_ROOT8.DIV.scale, value: '8', locked: true} - {id: CCM.CLOCK_ROOT8.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} - {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_OSC.OSC_24M} - {id: CCM_CLOCK_ROOT1_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT22_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT23_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT24_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT49_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT50_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT61_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT62_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT63_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT64_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT65_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT66_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT67_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT68_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT69_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT70_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT71_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT72_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT73_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT74_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT75_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT76_CONTROL_OFF_CFG, value: 'Off'} - {id: CCM_CLOCK_ROOT7_CONTROL_OFF_CFG, value: 'Off'} - {id: CLK_ROOT4_INIT_Config, value: disabled} - {id: OSC_RC_400M_CTRL3_EN_1M_CLK_CFG, value: Disabled} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ #ifndef SKIP_POWER_ADJUSTMENT #if __CORTEX_M == 7 #define BYPASS_LDO_LPSR 1 #define SKIP_LDO_ADJUSTMENT 1 #elif __CORTEX_M == 4 #define SKIP_DCDC_ADJUSTMENT 1 #define SKIP_FBB_ENABLE 1 #endif #endif const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { .postDivider = kCLOCK_PllPostDiv1, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ .loopDivider = 130, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ }; const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */ .pllDiv5En = 0, /* Enable Sys Pll1 divide-by-5 clock or not */ .ss = NULL, /* Spread spectrum parameter */ .ssEnable = false, /* Enable spread spectrum or not */ }; clock_pll_ss_config_t sysPll2SsConfig_BOARD_BootClockRUN = { .stop = 10000, /* Stop value to get frequency change */ .step = 1, /* Step value to get frequency change */ }; const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { .mfd = 20000, /* Denominator of spread spectrum */ .ss = &sysPll2SsConfig_BOARD_BootClockRUN,/* Spread spectrum parameter */ .ssEnable = true, /* Enable spread spectrum or not */ }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ void BOARD_BootClockRUN(void) { clock_root_config_t rootCfg = {0}; /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */ DCDC_BootIntoDCM(DCDC); #if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT) if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU)) { DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); } else { /* Set 1.125V for production samples to align with data sheet requirement */ DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V); } #endif #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE) /* Check if FBB need to be enabled in OverDrive(OD) mode */ if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); } else { PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); } #endif #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); #endif #if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT) pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; pmu_static_lpsr_dig_config_t lpsrDigConfig; if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) { PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); } if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) { PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); } #endif /* Config CLK_1M */ CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutDisable); /* Init OSC RC 16M */ ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; /* Init OSC RC 400M */ CLOCK_OSC_EnableOscRc400M(); CLOCK_OSC_GateOscRc400M(true); /* Init OSC RC 48M */ CLOCK_OSC_EnableOsc48M(true); CLOCK_OSC_EnableOsc48MDiv2(true); /* Config OSC 24M */ ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); /* Wait for 24M OSC to be stable. */ while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { } /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); /* * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code. */ /* Init Arm Pll. */ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); /* Init Sys Pll1. */ CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN); /* Init Sys Pll2. */ CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); /* Disable System Pll2 pfd0. */ ANADIG_PLL->SYS_PLL2_PFD |= ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK; /* Init System Pll2 pfd1. */ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 19); /* Init System Pll2 pfd2. */ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 16); /* Init System Pll2 pfd3. */ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 35); /* Init Sys Pll3. */ CLOCK_InitSysPll3(); /* Disable System Pll3 pfd0. */ ANADIG_PLL->SYS_PLL3_PFD |= ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK; /* Disable System Pll3 pfd1. */ ANADIG_PLL->SYS_PLL3_PFD |= ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK; /* Disable System Pll3 pfd2. */ ANADIG_PLL->SYS_PLL3_PFD |= ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK; /* Disable System Pll3 pfd3. */ ANADIG_PLL->SYS_PLL3_PFD |= ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK; /* Bypass Audio Pll. */ CLOCK_SetPllBypass(kCLOCK_PllAudio, true); /* DeInit Audio Pll. */ CLOCK_DeinitAudioPll(); /* Bypass Video Pll. */ CLOCK_SetPllBypass(kCLOCK_PllVideo, true); /* DeInit Video Pll. */ CLOCK_DeinitVideoPll(); /* Module clock root configurations. */ /* Configure M7 using ARM_PLL_CLK */ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; rootCfg.div = 2; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); CLOCK_PowerOffRootClock(kCLOCK_Root_M4); /* Configure BUS using SYS_PLL3_CLK */ rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; rootCfg.div = 2; CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); /* Configure BUS_LPSR using SYS_PLL3_CLK */ rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; rootCfg.div = 3; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); /* Configure CSSYS using SYS_PLL2_CLK */ rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out; rootCfg.div = 4; CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); /* Configure CSTRACE using OSC_24M */ rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); CLOCK_PowerOffRootClock(kCLOCK_Root_M4_Systick); /* Configure M7_SYSTICK using OSC_RC_400M */ rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M; rootCfg.div = 8; CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); /* Configure ADC1 using OSC_24M */ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); /* Configure ADC2 using OSC_24M */ rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); /* Configure ACMP using OSC_24M */ rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); /* Configure FLEXIO1 using OSC_24M */ rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); /* Configure FLEXIO2 using OSC_24M */ rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); /* Configure GPT1 using OSC_24M */ rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); /* Configure GPT2 using OSC_24M */ rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); /* Configure GPT3 using OSC_24M */ rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg); /* Configure GPT4 using OSC_24M */ rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg); /* Configure GPT5 using OSC_24M */ rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg); /* Configure GPT6 using OSC_RC_400M */ rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc400M; rootCfg.div = 6; CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg); /* Configure FLEXSPI1 using OSC_24M */ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE)) rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); #endif /* Configure FLEXSPI2 using SYS_PLL2_PFD2_CLK */ rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2; rootCfg.div = 3; CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg); CLOCK_PowerOffRootClock(kCLOCK_Root_Can1); CLOCK_PowerOffRootClock(kCLOCK_Root_Can2); CLOCK_PowerOffRootClock(kCLOCK_Root_Can3); /* Configure LPUART1 using OSC_RC_400M */ rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxOscRc400M; rootCfg.div = 6; CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); /* Configure LPUART2 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); /* Configure LPUART3 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg); /* Configure LPUART4 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg); /* Configure LPUART5 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg); /* Configure LPUART6 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg); /* Configure LPUART7 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg); /* Configure LPUART8 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg); /* Configure LPUART9 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg); /* Configure LPUART10 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg); /* Configure LPUART11 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg); /* Configure LPUART12 using OSC_24M */ rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg); /* Configure LPI2C1 using OSC_24M */ rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); /* Configure LPI2C2 using OSC_24M */ rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg); /* Configure LPI2C3 using OSC_24M */ rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg); /* Configure LPI2C4 using OSC_24M */ rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg); /* Configure LPI2C5 using OSC_24M */ rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); /* Configure LPI2C6 using OSC_24M */ rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg); /* Configure LPSPI1 using SYS_PLL2_PFD3_CLK */ rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3; rootCfg.div = 11; CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); /* Configure LPSPI2 using SYS_PLL2_PFD3_CLK */ rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3; rootCfg.div = 11; CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg); /* Configure LPSPI3 using SYS_PLL2_PFD3_CLK */ rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3; rootCfg.div = 11; CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg); /* Configure LPSPI4 using SYS_PLL2_PFD3_CLK */ rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3; rootCfg.div = 11; CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg); /* Configure LPSPI5 using OSC_24M */ rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg); /* Configure LPSPI6 using OSC_24M */ rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg); CLOCK_PowerOffRootClock(kCLOCK_Root_Emv1); CLOCK_PowerOffRootClock(kCLOCK_Root_Emv2); /* Configure ENET1 using OSC_24M */ rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); /* Configure ENET2 using SYS_PLL1_DIV2_CLK */ rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2; rootCfg.div = 4; CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); /* Configure ENET_QOS using OSC_24M */ rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg); /* Configure ENET_25M using OSC_24M */ rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg); /* Configure ENET_TIMER1 using OSC_24M */ rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); /* Configure ENET_TIMER2 using OSC_24M */ rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg); /* Configure ENET_TIMER3 using OSC_24M */ rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg); /* Configure USDHC1 using OSC_24M */ rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); /* Configure USDHC2 using OSC_24M */ rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); /* Configure ASRC using OSC_24M */ rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); CLOCK_PowerOffRootClock(kCLOCK_Root_Mqs); CLOCK_PowerOffRootClock(kCLOCK_Root_Mic); CLOCK_PowerOffRootClock(kCLOCK_Root_Spdif); CLOCK_PowerOffRootClock(kCLOCK_Root_Sai1); CLOCK_PowerOffRootClock(kCLOCK_Root_Sai2); CLOCK_PowerOffRootClock(kCLOCK_Root_Sai3); CLOCK_PowerOffRootClock(kCLOCK_Root_Sai4); CLOCK_PowerOffRootClock(kCLOCK_Root_Gc355); CLOCK_PowerOffRootClock(kCLOCK_Root_Lcdif); CLOCK_PowerOffRootClock(kCLOCK_Root_Lcdifv2); CLOCK_PowerOffRootClock(kCLOCK_Root_Mipi_Ref); CLOCK_PowerOffRootClock(kCLOCK_Root_Mipi_Esc); CLOCK_PowerOffRootClock(kCLOCK_Root_Csi2); CLOCK_PowerOffRootClock(kCLOCK_Root_Csi2_Esc); CLOCK_PowerOffRootClock(kCLOCK_Root_Csi2_Ui); CLOCK_PowerOffRootClock(kCLOCK_Root_Csi); /* Configure CKO1 using OSC_24M */ rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); /* Configure CKO2 using OSC_24M */ rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOsc24MOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); /* Set SAI1 MCLK1 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); /* Set SAI1 MCLK2 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); /* Set SAI1 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); /* Set SAI2 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); /* Set ENET Ref clock source. */ IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK; /* Set ENET_1G Tx clock source. */ IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK); /* Set ENET_1G Ref clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; /* Set ENET_QOS Tx clock source. */ IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK; /* Set ENET_QOS Ref clock source. */ IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK; /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK; /* Set GPT3 High frequency reference clock source. */ IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK; /* Set GPT4 High frequency reference clock source. */ IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK; /* Set GPT5 High frequency reference clock source. */ IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK; /* Set GPT6 High frequency reference clock source. */ IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK; #if __CORTEX_M == 7 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); #else SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4); #endif }

you can see that M4 is OFF, so if we change the code in this way

// CLOCK_PowerOffRootClock(kCLOCK_Root_M4); old code

/* Configure M4 using OSC_RC_400M */ enable clock CM4

rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc400M;

rootCfg.div = 1;

CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);

the M4 clock ON solves the issue.

Best regards

LPC Microcontrollers中的主题 Re: Cortex-M7 (IMXRT1171) crash

Cortex-M7 (IMXRT1171) crash

Re: Cortex-M7 (IMXRT1171) crash

Re: Cortex-M7 (IMXRT1171) crash

Re: Cortex-M7 (IMXRT1171) crash

Re: Cortex-M7 (IMXRT1171) crash

Re: Cortex-M7 (IMXRT1171) crash