LPC Microcontrollers中的主题 Re: LPC55S26 PIO0_5 FC4_RXD use, ISP disable

LPC55S26 PIO0_5 FC4_RXD use, ISP disable

alfredocyberhom — Mon, 23 Sep 2024 15:46:12 GMT

Hello, I'm working with a LPC55S26. I use the PIO0_5 pin as a UART4 receiver (FC4_RXD). The problem is that if this pin is low during reset (receiving data) it jumps to the ISP and my program doesn't start. Is there a way to disable the ISP function and make the pin work only as a UART4 receiver? I tried to write 0x70 in BOOT_CFG (0x9E400) but this didn't work.

Re: LPC55S26 PIO0_5 FC4_RXD use, ISP disable

Harry_Zhang — Thu, 26 Sep 2024 06:46:46 GMT

Hi @alfredocyberhom

Can you try to read the CMPA, Check if the writing is successful.

Hang

Re: LPC55S26 PIO0_5 FC4_RXD use, ISP disable

alfredocyberhom — Thu, 26 Sep 2024 12:48:28 GMT

I prepared the program image for the Cyclone (from PEMicro), setting bits 4-6 of BOOT_CFG (0x9E400) to one (0x70). I power up my board with PIO0_5 low and it hangs, it doesn't start. I connect in debugging with MultilinkUniversal (PEMicro) and verify that position 0x9E400 is set to 0x70. From what I understand from the LPC55S26 manual, during reset the CPU looks at pin PIO0_5 first of all, it would give the impression that if it is low it always enters ISP mode regardless of the bits in BOOT_CFG, but it is also strange that if so I don't find any sense in that PIO0_5 can be configured as UART reception.

Re: LPC55S26 PIO0_5 FC4_RXD use, ISP disable

alfredocyberhom — Thu, 26 Sep 2024 19:58:21 GMT

Re: LPC55S26 PIO0_5 FC4_RXD use, ISP disable

Harry_Zhang — Sun, 29 Sep 2024 06:20:36 GMT

Hi @alfredocyberhom

The problem arises because the boot mode selection (via PIO0_5 pin) takes precedence during reset, which causes the processor to jump to the ISP if the pin is low.

To work around this issue, you can prevent the processor from entering the ISP mode by ensuring the state of PIO0_5 is high during reset. Since PIO0_5 is being used as a UART4 receiver (FC4_RXD), you have a couple of options:
You can add an external pull-up resistor (e.g., 10kΩ to 3.3V) to the PIO0_5 pin. This will ensure that PIO0_5 is high during reset, preventing the processor from entering ISP mode.

Hang