topic Re: Reconfiguring SPI Interface from SPI Mode 2 to SPI Mode 0 in LPC Microcontrollers

Reconfiguring SPI Interface from SPI Mode 2 to SPI Mode 0

BM_ENG — Fri, 21 Jun 2024 14:05:01 GMT

Hello there,

I have a LPC546xx with the Flexcomm defined as SPI Interface. On the SPI interface I have a Master device which works with SPI Mode 2 (capture data at falling edge, default clock polarity High). This device can also work on SPI Mode 1.

On the same SPI Interface I have a Slave device with the CSn connected to the previous Master. This device works with SPI Mode 0.

From a sequence of 3-bytes on the SPI Bus, the Master reads the 1st-byte and enables the CSn for the Slave. Now with the CSn enabled from Master, the Slave device can be addressed. So the question is:
is possible to reconfigure the SPI Interface from SPI Mode 2(or perhaps 1) to SPI Mode 0 while keeping the SCK and CS from the SPI Interface enabled?

Re: Reconfiguring SPI Interface from SPI Mode 2 to SPI Mode 0

xiangjun_rong — Mon, 24 Jun 2024 05:35:44 GMT

Hi,

Can you tell us if the SPI of LPC546xx functions as master or slave?

If the spi of LPC546xx functions as master, it is easy to configure it as mode0 or mode1. After the current transfer has completed, you can reconfigure the CPOL/CPHA bit in the CFG register.

If the spi of LPC546xx functions as slave, during the /CS is high, you can reconfigure the CPOL/CPHA bit in the CFG register.

Hope it can help you

XiangJun Rong

Re: Reconfiguring SPI Interface from SPI Mode 2 to SPI Mode 0

BM_ENG — Mon, 01 Jul 2024 09:56:21 GMT

Thanks XiangJun Rong for your reply.

The SPI works as a Master and it has to send a transfer with 1 byte in Mode 1 and the rest of bytes in Mode 0, then the transfer is completed.
So the reconfiguration has to happen in the middle of a Transfer

regards

Re: Reconfiguring SPI Interface from SPI Mode 2 to SPI Mode 0

xiangjun_rong — Wed, 03 Jul 2024 07:48:43 GMT

Hi,

I suppose it is possible to change the master SPI mode, but you have to make sure that the mode changing happens while the master spi is idle.

1)You have to disable FIFO mode

2)when the transfer is over, the SPI transfer complete can trigger ISR, in the ISR, you can change the mode(CPOL/CPHA bits).

Pls have a try

XiangJun Rong