topic LPC55S69 (OKDO-E1 Board) SPI first CLK cycle twice long in LPC Microcontrollers

LPC55S69 (OKDO-E1 Board) SPI first CLK cycle twice long

maciek21 — Tue, 30 Jan 2024 14:36:58 GMT

Hi, trying to understand SPI on LPC55s69
Sent (0b10000000) over SPI MOSI to understand how it work, find out that first CLK cycle duty is twice as long as other.

Can anybody explain to my why and how can I fix that?
(Need identical time cycle to control addressed led)

#include <stdio.h> #include "board.h" #include "peripherals.h" #include "pin_mux.h" #include "clock_config.h" #include "LPC55S69_cm33_core0.h" #include "fsl_debug_console.h" #define TRANSFER_SIZE (1) /*! Transfer dataSize */ uint8_t masterRxData[TRANSFER_SIZE] = {0}; uint8_t masterTxData[TRANSFER_SIZE] = {0}; int main(void) { spi_transfer_t masterXfer; /* Init board hardware. */ BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); #ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL /* Init FSL debug console. */ BOARD_InitDebugConsole(); #endif /*Config transfer*/ masterXfer.txData = masterTxData; masterXfer.rxData = masterRxData; masterXfer.dataSize = sizeof(masterTxData); //masterXfer.configFlags = kSPI_FrameAssert; masterXfer.configFlags = 0; PRINTF("Debug start \r\n"); masterTxData[0] = 0b10000000; while(1) { SPI_MasterTransferBlocking(FLEXCOMM8_PERIPHERAL, &masterXfer); for(volatile int i=0;i<500000;i++); } return 0; }

Re: LPC55S69 (OKDO-E1 Board) SPI first CLK cycle twice long

Alex_Wang — Thu, 01 Feb 2024 09:37:49 GMT

Hi, @maciek21

For the first picture, it seems that the clock signal is incorrect, could you please show me all the signals of SPI?

How did you set up CPOL and CPHA? The picture is blurry and I can't see it clearly.

Best regards, Alex

Re: LPC55S69 (OKDO-E1 Board) SPI first CLK cycle twice long

maciek21 — Thu, 01 Feb 2024 20:53:52 GMT

hi, hope this time attache file will work

CPOL = 0
CPHA = 0

Re: LPC55S69 (OKDO-E1 Board) SPI first CLK cycle twice long

Alex_Wang — Fri, 02 Feb 2024 01:28:17 GMT

Hi, @maciek21

According to CPOL=0, the idle level is low, and CPHA=0 is rising edge sampling. While your logic analyzer shows falling edge sampling, you should choose the appropriate trigger edge. You can send me the screenshots of all SPI signals, including CLK, CS, MOSI and MISO.

Best regards, Alex

Re: LPC55S69 (OKDO-E1 Board) SPI first CLK cycle twice long

maciek21 — Fri, 02 Feb 2024 13:57:42 GMT

Hi, first, thanks for your help.

That's suggestion about CPOL and CPHA kind of answer my question and helped me find solution and fix problem.

The IDLE state for MOSI (and all other SPI signals) in this board is HIGH, as it is physically pulled-up to VCC by a resistor.

Due to this information, I should use CPOL = 1 and CPHA = 1 and that's worked.

I believe further investigation MISO, SSEL or SCK won't be necessary because I only need MOSI to control over led.

Have a good day