topic Re: LPC5528 USB1 Double Buffer Design in LPC Microcontrollers

LPC5528 USB1 Double Buffer Design

tks11111 — Wed, 06 Dec 2023 07:19:10 GMT

Hi all,

Based on the USB sample code dev_hid_generic_bm, we can see that the SDK enables double buffer by default. After studying for days, I found that this sample code uses producerOdd and consumerOdd to toggle the USB RAM buffer. But these flags are not HW registers.

My questions are:

1. How can I find out which one is the latest USB buffer in the USB RAM using the USB1 register (if the host sends two endpoint out to the same physical EP)? Can the EPTOGGLE register (Table 844) or the EPINUSE register(Table 839) help me to know which is the latest USB buffer in USB RAM if USB double buffer is full?

2. Is there a way that I can make USB double buffer fully filled?

Thanks.

BR,

Peter

Re: LPC5528 USB1 Double Buffer Design

xiangjun_rong — Fri, 08 Dec 2023 06:18:41 GMT

Hi,

This is the AE team reply:

"How can I find out which one is the latest USB buffer in the USB RAM using the USB1 register (if the host sends two endpoint out to the same physical EP)? Can the EPTOGGLE register (Table 844) or the EPINUSE register(Table 839) help me to know which is the latest USB buffer in USB RAM if USB double buffer is full?

User can use "USB EP Buffer in use" detect which buffer in use

2. Is there a way that I can make USB double buffer fully filled?

set the max transfer size in descriptor, and make sure the HOST side can reach the max transfer size.

XiangJun Rong

Re: LPC5528 USB1 Double Buffer Design

tks11111 — Fri, 08 Dec 2023 07:15:10 GMT

Hi XiangJun,

Do you have a document that explains the detailed double buffer design? I know double buffer can enhance the USB transfer efficiency but I'm not sure how it works.

As we know, once the active bit is cleared by the HW, it will trigger the USB interrupt and let us know which EP has the data coming in or out. Meanwhile, the HW will toggle the EPINUSE to get ready for the next same EP data transfer. My guess is that once it triggers the USB interrupt, the HW is ready for the next data. Am I correct?

Thanks.

BR,

Peter

Re: LPC5528 USB1 Double Buffer Design

xiangjun_rong — Mon, 11 Dec 2023 09:30:31 GMT

Hi,

I suppose that there is not dedicated doc which focuses on the USB double buffer design.

This is the USB buffer architecture:

For the double buffer design, for each logic endpoints, for the input buffer, there are two buffer for each ENDPOINT IN, for out buffer, there are two buffers.

So each logic end points will like:

IN buffer for each logic endpoint.

CS NBYTES Offset1

CS NBYTES Offset2

OUT buffer for each logic endpoint.

CS NBYTES Offset3

CS NBYTES Offset4

Hope it can help you

XiangJun Rong