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    <title>topic Re: Flash Corruption of LPC546 Processor On Power Down in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Flash-Corruption-of-LPC546-Processor-On-Power-Down/m-p/1759583#M54749</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;From hardware perspective, when you erase/program flash, the current will increase, so it is possible that the power supply voltage will decrease, I suggest you use a LDO or DC/DC converter which can provide enough current.&lt;/P&gt;
&lt;P&gt;From software perspective, I suspect that you have the code to erase/program flash in your application code, as you know that flash operation instruction is saved in ROM and run in ROM, when you erase/program flash, you must disable all interrupt, disable watchdog lest the flash code is executed.&lt;/P&gt;
&lt;P&gt;I copy the section from UM10912.pdf&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;section 5.6 In-Application Programming&lt;/P&gt;
&lt;P&gt;The flash memory is not accessible during a write or erase operation. IAP commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP flash programming is permitted in the application.&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Hope it can help you&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
    <pubDate>Mon, 20 Nov 2023 06:11:42 GMT</pubDate>
    <dc:creator>xiangjun_rong</dc:creator>
    <dc:date>2023-11-20T06:11:42Z</dc:date>
    <item>
      <title>Flash Corruption of LPC546 Processor On Power Down</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Flash-Corruption-of-LPC546-Processor-On-Power-Down/m-p/1757725#M54711</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello, I've been working with a LPC54616J512ET100 microprocessor and am stumped with a particular issue. Occasionally, when I power cycle the microprocessor, a portion of the flash memory will be corrupted. I suspect that this perhaps has to do with the LPC attempting to write to the eNVM without proper input voltage. I've experimented with adding a voltage supervisor to alert the LPC that voltage is dropping via an interrupt. The interrupt sets a flag which prohibits any any writes to the eNVM. Any suggestions regarding ideas to preserve the eNVM between power cycles would be greatly appreciated.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 15 Nov 2023 15:22:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Flash-Corruption-of-LPC546-Processor-On-Power-Down/m-p/1757725#M54711</guid>
      <dc:creator>dbresciaNAII</dc:creator>
      <dc:date>2023-11-15T15:22:33Z</dc:date>
    </item>
    <item>
      <title>Re: Flash Corruption of LPC546 Processor On Power Down</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Flash-Corruption-of-LPC546-Processor-On-Power-Down/m-p/1759583#M54749</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;From hardware perspective, when you erase/program flash, the current will increase, so it is possible that the power supply voltage will decrease, I suggest you use a LDO or DC/DC converter which can provide enough current.&lt;/P&gt;
&lt;P&gt;From software perspective, I suspect that you have the code to erase/program flash in your application code, as you know that flash operation instruction is saved in ROM and run in ROM, when you erase/program flash, you must disable all interrupt, disable watchdog lest the flash code is executed.&lt;/P&gt;
&lt;P&gt;I copy the section from UM10912.pdf&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;section 5.6 In-Application Programming&lt;/P&gt;
&lt;P&gt;The flash memory is not accessible during a write or erase operation. IAP commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP flash programming is permitted in the application.&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Hope it can help you&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
      <pubDate>Mon, 20 Nov 2023 06:11:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Flash-Corruption-of-LPC546-Processor-On-Power-Down/m-p/1759583#M54749</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2023-11-20T06:11:42Z</dc:date>
    </item>
    <item>
      <title>Re: Flash Corruption of LPC546 Processor On Power Down</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Flash-Corruption-of-LPC546-Processor-On-Power-Down/m-p/1764064#M54799</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;XiangJun,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you for your swift response!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I have good confidence that our system has a capable DC/DC converter providing power to the LPC uP.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;But I will take your advice and ensure that all interupts are disabled during writes to the flash.&amp;nbsp; I will also make sure that the first 32 bytes of RAM are used only by the flash routines.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank You,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Dan Brescia&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 27 Nov 2023 13:44:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Flash-Corruption-of-LPC546-Processor-On-Power-Down/m-p/1764064#M54799</guid>
      <dc:creator>dbresciaNAII</dc:creator>
      <dc:date>2023-11-27T13:44:16Z</dc:date>
    </item>
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