[LPC5536]Slow system on higher clock

ja_lpc — Fri, 13 Oct 2023 07:17:32 GMT

When I configure the [LPC5536] to run its main clock on FRO 96MHz, then the system runs faster than that of the when we configure it to run on 150MHz(via PLL) ?

This above observation is concluded based on timestamps from the console logs (and its consistent).

The code being used for 96MHz

POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
CLOCK_SetupFROClocking(12000000U);
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);

CLOCK_SetupFROClocking(96000000U);

POWER_SetVoltageForFreq(96000000U);
CLOCK_SetFLASHAccessCyclesForFreq(96000000U);

CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);

The code being used for 150Mhz via PLL0:

POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
CLOCK_SetupFROClocking(12000000U);
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);

CLOCK_SetupExtClocking(16000000U); /* Enable XTALHF clock */
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */

POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */

/*!< Set up PLL */
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
const pll_setup_t pll0Setup = {
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
.pllndec = SYSCON_PLL0NDEC_NDIV(8U),
.pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
.pllRate = 150000000U,
.flags = PLL_SETUPFLAG_WAITLOCK
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */

/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */

/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */

Re: [LPC5536]Slow system on higher clock

xiangjun_rong — Fri, 13 Oct 2023 09:21:36 GMT

Hi,

This is the FRO 96mHz accuracy, it can reach up to 96.96mhz at most.

I copy it from data sheet of LPC553x.

Hope it can help you

XiangJun Rong

Re: [LPC5536]Slow system on higher clock

danielholala — Fri, 13 Oct 2023 10:40:18 GMT

How exactly are you measuring "speed" of you system?

Re: [LPC5536]Slow system on higher clock

ja_lpc — Fri, 13 Oct 2023 11:41:06 GMT

Hi,

I am switching from internal FRO to external via PLL (internal 96MHz to 150MHz.)

But my logs were showing contradicting timestamp values.

Re: [LPC5536]Slow system on higher clock

ja_lpc — Thu, 19 Oct 2023 11:24:40 GMT

I was able to get the expected timestamps after correcting the systick according to main clk

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