topic Re: LPC55S69 SRAMs dual-ported? in LPC Microcontrollers

LPC55S69 SRAMs dual-ported?

raz3l — Wed, 23 Aug 2023 13:49:52 GMT

Hi,

I'm doing a study on contention on the LPC55S69 architecture. Could someone clarify me if the the SRAMs in this board are dual-ported?

Re: LPC55S69 SRAMs dual-ported?

Xu_Zhang — Thu, 24 Aug 2023 09:08:18 GMT

hi,raz3l

Can you further describe your question about what the LPC55S69 does and what dual port means and is used for? To help you in more detail.

Xu Zhang

Re: LPC55S69 SRAMs dual-ported?

raz3l — Thu, 24 Aug 2023 10:42:41 GMT

Hi @Xu_Zhang ,

By "dual-ported SRAMs," I mean if the SRAM memory elements for data (SRAM0-SRAM3) allow for two independent read or write operations to occur simultaneously. In the context of the LPC55S69, my concern is whether both cores of the microcontroller can access the SRAM concurrently, without causing contention or access conflicts.

In simpler terms, I'm trying to determine if the LPC55S69's SRAM architecture supports simultaneous read and write operations from both cores (e.g., the main core and the co-processor core) without one core blocking the other.

Thank you!

Re: LPC55S69 SRAMs dual-ported?

Xu_Zhang — Mon, 28 Aug 2023 08:51:03 GMT

hi,raz3l

To achieve the best working performance, allocate the memory blocks of code and data for both cores in a suitable way and reduce the arbitration of the accessing bus in the hardware system.
In the hardware system diagram, the memories are divided into blocks and connected to the AHB bus matrix separately. Using this design, different bus masters can access different memory blocks simultaneously, without any arbitration delay.

Xu Zhang

Re: LPC55S69 SRAMs dual-ported?

raz3l — Mon, 04 Sep 2023 10:28:31 GMT

Hi @Xu_Zhang,

I appreciate your suggestion regarding memory allocation and bus access optimization, which I already suspected and tested. However, my inquiry stems from a more in-depth examination of the microarchitecture of the LPC55S69 board as part of my research on contention in various NXP platforms. That's why I specifically asked which if the organization of the SRAM is single- or dual-ported, something that could justify some of the results that I'm getting.

Thank you!

Re: LPC55S69 SRAMs dual-ported?

Alice_Yang — Tue, 05 Sep 2023 08:36:29 GMT

Hello @raz3l

The SRAM in lpc55ss69 is not dual-ported, while if you want to share SRAM between two cores, you can refer to SDK demo "lpcxpresso55s69_erpc_matrix_multiply_rpmsg"

Alice

Re: LPC55S69 SRAMs dual-ported?

raz3l — Tue, 05 Sep 2023 08:41:06 GMT

Thank you Alice!