LPC MicrocontrollersのトピックSDRAM Layout guideline

SDRAM Layout guideline

lpcware — Wed, 15 Jun 2016 17:57:35 GMT

Content originally posted in LPCWare by schisanoa on Tue Jun 24 02:34:10 MST 2014
Hi, do someone know if there is an Application Note that explain how to make a correct layout?

I'm interfacing a 32Bit SDRAM, ISSI IS42S32800D-7BL, and I will work at 60MHz

the DataLine must have the same length?
is there some rule for clock routing?
address and command line should have the same length of dataline?

thanks
Ale

Re: SDRAM Layout guideline

lpcware — Wed, 15 Jun 2016 17:57:36 GMT

Content originally posted in LPCWare by mc on Tue Jun 24 07:11:18 MST 2014
Hi Ale,
LPC177x_8x SDRAM interface works similar to LPC18xx. Please refer to below app note.
http://www.nxp.com/documents/application_note/AN11508.pdf

LPC177x_8x also have a delay line for fine tuning the EMC timings(flight time etc). Please check EMCDLYCTL register in the user manual.

You can also check below app note for layout of data,command lines
http://www.nxp.com/documents/application_note/AN10935.pdf

Re: SDRAM Layout guideline

lpcware — Wed, 15 Jun 2016 17:57:36 GMT

Content originally posted in LPCWare by schisanoa on Tue Jun 24 07:57:05 MST 2014
Thanks MC, I've already found the documents that you suggest, but I have a question.

My configuration is with only 1 SDRAM connected on the bus, I matched the impedance suggested in the doc and also the layer stackup.

The question is: looking the first document, at page 19, section 2.7, is suggested to keep "bus signals as short as possible and capacitive loading to a minimum", and after this, there is the Rule 1, that talk about net length, but if I have correctly understant is referred to multiple SDRAM configuration, that is not my configuration and the document never talk about single SDRAM data, address or command line wire length.

From this I suppose that with single SDRAM is not required to match the data bus wire length by using of meanders, is it correct?
And if it is, why if I look at the LPC1788 OEM Board from EA seems that they used meanders to match the data ram signal?

Sorry if my question is a little confused, ask me if it is not clear

Re: SDRAM Layout guideline

lpcware — Wed, 15 Jun 2016 17:57:37 GMT

Content originally posted in LPCWare by SimonThome on Wed Jul 01 00:13:47 MST 2015
Hi there,

Does anyone have an answer to the question above? RE: What is the length matching requirements when only a single SDRAM device is used with either the LPC17xx or LPC18xx?

Thanks