ECRP codeprotect simulation on LPC5526

bwinter — Sat, 11 Mar 2023 09:47:29 GMT

Unit now i only used NXP controllers with single bit or multi-bit ECRP code protection.

It seems the LPC5526 (non S) is very different and to me a little confusing at the moment.
I just want to lock out (all debug) options through the SWD port and readout/update through the serial UART port. Full erase (uart) would be nice but ONLY if it also erases the full protection (and that seems to be not true, leaving the unit bricked/un-programmable)

The device has to have an option to update through the serial port (ISP) after protect, so i want to reverse the protection

Idea now is to lock the device after testing under program control (done by my internally firmware) (EnableFlashProtect ) and have an option to unlock the complete device after having received the right challenge response key (done by my internally firmware) (DisableFlashProtect )

Can this be done? (meaning protection is not OTP)

NXP has a demo with a DisableFlashProtect and EnableFlashProtect part.
difference between both is (disable):

/* Clean-up CMPA area */ g_CMPAData[4] = 0; // 4 and 5 must clean same time g_CMPAData[5] = 0;

and (enable) (comment is source seems different from real value!):

// Erase Dis - ISP Dis - JTAG Dis - DGBEN Dis - NIDEN uint16_t CMPAData = 0x0000; // (0 << 8 | (1 << 6) | (1 << 4) | (1 << 1) | (1 << 0); uint16_t CMPADataReverse = ~CMPAData; uint32_t CMPALockData = (CMPADataReverse<<16)|(CMPAData); g_CMPAData[4] = CMPALockData; // 4 and 5 must set as same value g_CMPAData[5] = CMPALockData;

Is this all we have to set and reset?
Looking at the values above it makes no sense, in the unprotect version the low value is 0 and the inversed high part is also 0. The protect version also writes (low) 0 and does the inversed high part.

Secondly in an other post i found that the above is only for SWD? and not blocking the access though the UART ISP method (holding p0.5 low on startup), meaning it's "useless". For that i should change boot options?
Just want the ECRP compatible settings.

If i get it right operating this way keeps me in "Tier1" Dev mode allowing changes.

I also seem to be missing the bit definitions in the UM11126.pdf manual.

Re: ECRP codeprotect simulation on LPC5526

Alice_Yang — Mon, 13 Mar 2023 08:10:22 GMT

Hello @bwinter

There is a demo about disable SWD and ISP , you can refer to.

About "bit definitions in the UM11126.pdf manual.", please see excel in attachment of UM.

topic ECRP codeprotect simulation on LPC5526 in LPC Microcontrollers

ECRP codeprotect simulation on LPC5526

Re: ECRP codeprotect simulation on LPC5526